Altera has developed the industry’s first low power FPGAs with anti-tamper, design security, and design separation. Extending low-power leadership, these low power FPGAs offer double the resources for less than 0.25W!
The Cyclone III LS devices offer up to 200K LEs for less than 0.25W of static power. It is said to be targeting power- and board-space-sensitive applications in all market segments. “Any market that requires low power and security features will require this product,” said Ms Susan Chang, AP marketing manager for Cyclone Series, Altera, underlining the growing importance of low-power FPGAs into power-constrained applications. The devices are shipping to customers now.
A closer look at the Cyclone III LS FPGAs reveals the following:
Low power: 200K LE (logic elements) for under 0.25W; TSMC 60nm low-power (LP) process; and Quartus II software power-aware design flow.
* Information assurance design suite: Offering data protection for information-assurance applications, features include anti-tamper, design security, design separation and IP, design examples, etc.
* High functionality: Featuring densities ranging from 70K to 200K LEs; up to 8.2 Mbits of embedded memory; and up to 396 embedded multipliers.
The Cyclone III LS FPGAs are said to have the most comprehensive IP protection in an FPGA. It protects the IP with anti-tamper and design security. “There is a JTAG port protection to prevent reverse engineering,” Chang added.
Security features include CRC to monitor for configuration changes, zeroizing the device if tampering is detected, and an on-chip oscillator that acts as an uninterruptible clock source for system monitoring.
Design separation features include single-chip redundancy and supporting information-assurance applications. This leads to reduction in power and board space, as well as reduction in BOM (bill of materials) cost — by about 50 percent.
Yet another feature is that of data assurance with design separation. Designers can now create physically isolated partitions with design separation. This protects against time-dependent faults and SEU, and increases the system uptime as well. These enable achieving a higher level of integration on a single device.
Military market and SDR
According to Chang, the military market will be among the most important ones for these devices. Hence, Altera’s clear thrust on design security and prevention of reverse engineering!
Focusing on the size, weight, and power (SWaP), these will support next-generation SDR waveforms with small footprint and low power (e.g., MUOS, SRW), night-vision goggles, and secure communications. It features crypto-modernization moving toward standardization.
The Cyclone III LS devices also support existing SDR (software-defined radio) applications. Chang said that SDR is one common design trend in the military market.
The next-generation software-defined radio (SDR) waveforms require more memory and logic for networking in the field and low power for extended battery life. Some other key requirements include small footprint for board space, data security for multiple channels in a single chip, and IP security and anti-tamper.
As far as the next-generation SDRs are concerned, these devices will facilitate reduction of the overall board space by up to 50 percent, an increase in the battery life by up to 2X, besides facilitating a single-chip secure SDR solution.
Nearly 17 months ago, I’d discovered FPGA Central! This discovery has gone one better — introducing the FPGA Seek (www.fpgaseek.com)!
According to the site, the FPGA Seek is a search engine optimized for field programmable gate array (FPGA) and CPLD’s related topics. FPGA Seek brings together the search engine technology from Google but with a laser focus on results related to FPGA/CPLD.
This search engine only goes on to show the importance FPGAs have been gaining. Even the open source world hasn’t been far behind. Recently, Altera’s Nios II processor received Wind River Linux support. And just before that, both Xilinx and Altera chose to release products the same day!
FPGA related jobs
Of course, there’s a whole lot of information on this site. Users can also suggest a site they’d like to be added. There’s also a link to FPGA and CPLD related jobs. Of course, it opens on to the FPGA Job Central page. In fact, a lot of jobs have been posted in the recent days. So, those looking for openings, do check it out.
I’ve been also conducting several searches on the site and am delighted to find several references to my articles/blog posts. 🙂
Enough said… perhaps, you should all check out and bookmark FPGA Seek! Lastly, thanks to FPGA Central for letting me know!!
This post is based on a presentation recently made by Amit Dhir, Senior Director, Business Operations, Xilinx, prior to the launch of the Xilinx Virtex-6 and Spartan-6 FPGA families. Xilinx was very kind to share this with me, and I need to thank him and Neeraj Varma, Country Manager – Sales (India/ANZ) for Xilinx.
Xilinx’s next-generation FPGA families are said to enable new, targeted design platforms. Incidentally, Altera, too, decided to launch its Stratix IV GT and Arria II GX FPGAs, the same day as Xilinx.
Back to Dhir’s discussion on the programmable imperative and a changing semiconductor landscape! According to him, the key market trends changing the technology landscape include the empowered consumer, hyper-connectivity and social networking. In this scenario, time-to-market and flexibility are the key attributes for success.
Customer challenges today revolve around doing more with less, and now! Companies now need to monitor their market and competitive leadership, time-to-market and profitable growth, spiraling development cost, and risk aversion and product complexity. Business constraints are now forcing customers to reduce internal R&D investments. The graph shows the IC cost by process nodes.
Time for programmables NOW!
The time for programmables is now! It is an ideal technology to help combat customer challenges. The programmable imperative is driven by factors such as market forces, financial constraints and technology drivers. Really, it all boils down to accelerating the programmable imperative!
Looking back at the logic IC landscape, business dislocation has been underway for the incumbents. From 1998 through 2004, a significant amount of IP migrated from system OEMs to ASSP vendors, particularly in the communications market.
Even ASICs present a bleak outlook and are likely going the way of gate arrays! The graph here shows the declining ASIC market share.
The increasing development costs and reduced R&D investments by OEMs has been leading to accelerated erosion of ASIC market share going forward. In fact, the long-awaited tipping point where FPGAs replace gate arrays is upon us.
ASSP vendor challenges
Looking at ASSP vendors, those vendor in tier 1 face challenges such as business model viability and poor profitability. High risk environment leads to poor customer loyalty. The large capital outlay on fabbed is moving on to fablite and fabless. Next, market and customer consolidation means fewer deals for such vendors. Chase of >1M units means few applications and customers.
What about the tier 2 ASSP vendors challenge? They have been forced into very high volumes and compete poorly against the tier 1 vendors. Hence, profitability and business models are under severe pressure. It is to be noted that out of the 115-odd companies followed by the GSA (Global Semiconductor Alliance), 29 have market caps less than their cash.
As for the tier 3 ASSPs and startups challenge, the Round-A VC funding has dried up! Incidentally, the round-A funding (dollar amount) declined 82 percent from 2000 and 2007. Through Q308, only two chip companies received round-A funding, totaling $12 million.
Programmables next business disruption
Looking at the logic IC landscape, programmables are emerging as the next business disruption. FPGAs are no longer seen as a yearly cost burden prior to ASIC release, but more as a solution that could live in products and platforms over time.
The tipping point should happen in 2009, and programmables should reach a plateau of productivity by 2016!
Where Xilinx fits in!
Today, Xilinx sees growth opportunity ahead, and it is more of a pragmatic reality now! The company understands that new attributes are required to meet the challenges of the future. It lists three attributes to bring about this change:
* Transformation: Market led, semiconductor leader.
* Ushering in the era of targeted design platforms.
* World class, thriving third-party ecosystem.
Transformation is already underway at Xilinx, which is now becoming a market led, semiconductor business leader.
It is ushering in the era of targeted design platforms, which is enabling innovation. A view at the ASIC/ASSP class applications reveals that the positioning has become more market focused. The architecture is more toward market tuned platforms. Xilinx also focuses on low power leadership. Its design methodology has now become open, scalable and hierarchical.
Targeted design platforms also enable customers to do more, and faster, and focus on their differentiation! Xilinx also boasts a world class and thriving third-party ecosystem. The software and IP is scalable, standardized, extensible and collaborative.
Xilinx is striving to accelerate the programmable experience by giving what customers need, and when they need it! Its Virtex and Spartan silicon form the programmable foundation. It offers base targeted design platforms — devices, software, IP, boards, etc. It also offers domain specific platforms, along with domain specific IP and tools, as well as market specific platforms, which are inclusive of market specific reference designs and IP.
According to Dhir, the company is offering innovative technology to address diverse market requirements and to drive programmable logic beyond the tipping point!
Hardly any segment of the global semiconductor industry has escaped the economic financial crisis! Nevertheless, as the year draws to a close, several segments are planning strategies for tackling what could well be a difficult 2009! FPGAs are no exception!
Jennifer Lo, Senior Marketing Manager, Altera Asia Pacific, agrees. Highlighting the impact, as per reports in the media, the economical environment we are getting into is extremely challenging. Recently, Gartner lowered its 2009 semiconductor forecast to ‘down 16 percent’ as compared to 2008.
Altera placed strongly
Lo says that compared to the other semiconductor companies, many of whom are taking very drastic measures in cutting down costs and preserving capital, Altera is in a very strong position, both financially and product-wise.
Financially, Altera is said to have taken steps to focus on cost reductions and simplification internally, a few years ago. The company is seeing great results from those efforts. “You may check our financial data and find that we are essentially debt-free and have very healthy balance sheet. We continue to be profitable even under the very challenging environment we are in,” Lo contends.
Product-wise, Altera announced a few days ago that it is shipping the industry’s 40nm product, considered a key milestone. “We are very excited about it with this new product family, Stratix IV, which offers the industry’s largest density, highest performance, highest system bandwidth and lowest power, targeting customers in a variety of markets, including communications, broadcast, test, medical and military,” she says.
Going forward in 2009, Altera will continue to rollout the rest of the members in the Stratix IV product family. It will also continue to execute new product strategies in the plan with full confidence.
Tackling demand weakness in FPGAs
There have been whispers regarding demand weakness in the FPGA industry. On the contrary, Lo adds that lower power, lower cost and smaller space are still common needs for portable applications for 2009. These needs may drive PLD vendors to focus on architecture and process to address power and cost. Also, work on package to develop a smaller device. Altera’s goal is to still focus on these common needs.
The Altera MAX II Z already offers the lowest dynamic power and comparable static power in industry already. The company may focus more on package size on 2009.
Although leading-edge FPGAs are scaling to 40nm and beyond, have the tools caught up with these new and complex processes? She says that lowering power consumption and improving customer productivity have been the focus of Altera’s product strategies for the past few years.
Lo adds: “Lowering power consumption means lowering costs for customers, not only in the BOM cost (reducing heatsink or cooling requirement), but also the ongoing operating cost (fans, air-conditioning costs,…etc). At this day and age of ever increasing fuel and electricity costs, this is gaining significance in customers’ selection consideration. Seeing such a need, reducing device power consumption has been a major element in the company’s product planning and execution.”
Altera’s Max II Z product in the low-cost CPLD line offers the lowest dynamic power and static power in the industry that is catered for the portable applications. On the high end of the spectrum, with Stratix IV GX, for example, with the advanced 40nm process node, Altera utilizes the ‘Strained Silicon’ technology, lower core voltage of 0.9V, triple gate oxide, as well as low-K inter-metal dielectric material low power transceiver designs.
“In terms of design, we put in extra effort in lowering the overall power consumption in the transceivers as well as optimized DDR memory interfaces,” she notes.
Coupled with programmable power technology, which allows customers to use high performance (hence, high power consumption) circuitry for design along the critical path, while either using low-power circuit on other parts of the design or turning the logic blocks completely off while not in use, all process and design innovations work together toward one common goal of lowering the overall power consumption in the customer design.
Lo says: “In customer productivity improvement, we’ve invested in the feature sets in our design software, Quartus II, to enable team-based designs, incremental compilation, as well as faster compilation time compared to the other competing software. We also have a wide suite of IPs in a multitude of applications and technologies, such as our Nios embedded processors, the many memory interfaces and peripherals. Combining all of those with our SOPCBuilder tool also enables customers to integrate system designs with very much reduced time and effort.”
There have also been some talks lately about FPGA design starts being quite flat over the last couple of years.
Altera sees a lot of new market applications for FPGAs, apart from the traditional communications market. Out of the many market segments that it participates in, the company feels that communications, military and industrial segments will be in better situation than others in the next couple of years. Needless to say, Altera will continue to focus on these segments.
Tackling complexity is a major focus area for projecting FPGAs as a growth segment for 2009.
Lo says: that as with other previous downturns, the industry may go through its reformation, which may inevitably involve some weaker companies to either go out of business due to deteriorating business environment or get acquired by stronger companies. Altera is very confident that programmable logic, with its highly flexibility, versatile application, will have a good market position in 2009.
The Hardcopy ASIC is said to have been Altera’s major differentiator from the other PLD/FPGA vendors.
“We are the only company having both an FPGA vehicle to enable fast time-to-market and simultaneously possessing the seamless migration platform to low-cost production support using Hardcopy ASIC. With the industry trend of fewer and fewer ASIC starts due to the high NRE costs and high justifying volume, there will also be less investment in the ASSP front given the contracting demand. We see Hardcopy as a major competitive edge that will us bring to a different rank in the industry,” she notes.
Indeed, it is good to see companies thinking very hard about tackling a difficult 2009! There’s lot of fight left, and it’s not that semiconductor companies haven’t faced downturns earlier. Keep the faith and allow these folks to come up tops again!
Turning my attention to the programmable logic market, I took advantage of my recent meeting with Jordan Plofsky, Senior Vice President Market, Altera Corp., during the Altera SOPC conference.
Programmable logic consumption in India has been estimated at between $20-$25 million in 2008, largely driven by strong growth in communications infrastructure and increased spending in the military sector. The Indian programmable logic market is likely to grow at a CAGR of 25 percent over the next three years.
Altera’s India strategy
In this context, it will be interesting to note Altera’s strategy within the Indian semiconductor industry.
Plofsky says that as multinational companies are transferring more design work to their R&D teams in India, local companies are expanding their range of products, and independent design service companies are capturing a bigger piece of the outsourced design pie, Altera forecasts the increased need for high quality application support.
He says: “Unlike other companies who have design services operations in India, which compete with the local independent design services, our strategy is to partner with the local India design services industry. We are expanding our direct and indirect support channels to provide higher quality services to our customers here.”
Altera is also supporting the development of the education sector in India, which is modernizing to turn out well trained engineers to satisfy the appetite of the industry. “We also run industrial workshops and seminars, like the recent SOPC World in Bangalore and New Delhi, to educate the design community on the direction of semiconductor technology,” adds Plofsky.
Altera has also set up Altera Joint Laboratories in leading universities across India to provide a better platform for undergraduates to grasp basics of programmability.
Role in solar?
With investments in solar/PV happening, is there a role for Altera and other FPGA companies? This is a question that I invariably ask everyone in the semiconductor industry!
According to Plofsky, one of the promising applications is smart metering. It is the practice of getting the users and the infrastructure to be power aware and then using different usage patterns to lower energy usage and energy costs by applying smart algorithms.
Addressing low-power design
Power consumption has always been a big concern for designers in all markets and Altera has a number of different solutions.
In the CPLD area, Altera announced its zero power MAX IIZ devices in late 2007. Offering the highest density and I/O count in packages as small as 5x5mm, compared to macrocell-based CPLDs, MAX IIZ devices allow designers to meet changing functional requirements and lower power while saving board space.
Consuming 75 percent less power than competing FPGAs, the Altera Cyclone III devices are the industry’s first and only 65-nm low-cost FPGA family, and offer digital system designers an unprecedented combination of density, power and cost.
To address the low-power demands of high density customers, the Stratix III and Stratix IV family members feature Altera’s patented Programmable Power Technology. This power-saving technology optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design. And in addition these designs can be converted to HardCopy ASIC devices that can reduce power consumption by 50-70 percent.
As for new products in the LTE, TD-SCDMA and NFC spaces, Plofsky says that with the new 40-nm devices, Altera is uniquely positioned to deliver solutions that provide the density, performance and power for these emerging applications. The combination of DSP blocks, memory and transceivers was optimized for these communication applications.
Altera just announced its 40nm devices in May and it is said to be on target to deliver those devices by the end of 2008.
Adds Plofsky: “We have already started development work on smaller process geometries with test chips in fab now, but it is too early to go into any family detail at this time.”
How true! Field programmable gate arrays or FPGAs have become faster, denser and more complex over the years!
Speaking at the recently held Altera SOPC conference, S. Janakiraman, President and CEO-R&D Services, MindTree, and former chairman, India Semiconductor Association (ISA), said these had found acceptance in a wide range of market segments. “FPGAs are everywhere, be it telecom or industrial or medical,” he added.
Once relegated to simple glue logic design, FPGAs are challenging SoCs today. The million-gate FPGAs are, in fact, quite common. What’s more, ASSP like features, for example, PCI Express, USB, etc., have also found their way into FPGAs.
FPGAs have adopted Moore’s Law more closely than any other device technology! They even ‘help’ in ‘ratifying’ new process nodes.
Janakiraman said: “With the ever increasing costs of designs and declining ASIC starts, FPGAs offer a considerably less riskier approach, development costs, tools and testing – even at latest technology nodes.”
So what would be the factors driving change? These are multiple, and actually split into cost, performance, time-to-market and also field-upgradeable hardware.
From the cost aspect, functions in a system with standard ICs are performed by dedicated discrete components on a PCB. The FPGA route can reduce routing congestion and lower costs by enabling the use of smaller boards with less layers and lower component count.
Next comes performance, and a key factor in accelerating performance is parallel implementation. Here too the FPGA can be easily programmed to handle the same sequential instruction set by leveraging multiple micro-CPUs, connected by very wide internal buses.
Time-to-market has obviously become critical with the consumerization of electronics. As a result, the FPGAs are increasingly entering this segment because of the obvious advantages of early product introductions.
As for the field upgradeable hardware, Janakiraman elucidated an example: configuring video capture card for Europe (PAL), NA (NTSC), JAPAN (SECAM), need one hardware configuration with an FPGA on it. Depending on the location end-user downloads country specific driver that configures FPGA accordingly.
Jani Sir, as he is affectionately known, delivered the keynote at the Altera SOPC, which really touched upon how a fabless India was shining.
I also managed to catch up with Jordan Plofsky Senior Vice President Market, Altera. All I can add here as a sneak peek is: uncertainty favors FPGA’s usage! Let’s see how true — in my next blog!