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Global semiconductor companies delivering platforms: Jaswinder Ahuja, Cadence


Jaswinder Ahuja.

Jaswinder Ahuja.

Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well and alive. The organization has been aligned around the EDA360 vision.

The EDA360 is a five-year vision for defining the trends in the EDA industry, based on what Cadence is observing in the industry and the direction in which, it feels, the industry will go.

At Cadence,  the Silicon Realization Group is headed by Dr. Chi-ping Hsu. The SoC Realization Group is headed by Martin Lund, and Nimish Modi is looking after the System Realization Group. Cadence’s focus has been on in-house development and innovation. Tempus has been a major announcement from the Silicon Realization Group.

What’s going on with EDA360?
There has been a renewed thrust in the SoC Realization Group at Cadence. Already, there have been three acquisitions this year — Cosmic Circuits, Tensilica and Evatronix. Cadence is buying the IP part of the business from Evatronix. This acquisition is ongoing and will be announced in June 2013.

On the relationship between the electronics and the EDA industries, Ahuja said the electronics industry is going through a transition, and that the EDA industry needs to change. The importance of system-level design has increased. Companies are currently focusing on optimizing the end user experience.
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Cadence Tempus accelerates timing analysis and closure by weeks!

May 24, 2013 Comments off

Cadence Design Systems Inc. has announced the Tempus timing signoff solution. It facilitates ground-breaking signoff timing analysis and closure. The new technology accelerates timing analysis and closure by weeks. It is said to be up to 10X faster than competing solutions. Tempus has also been endorsed by Texas Instruments (TI).

TempusComplexity is growing exponentially and signoff is the bottleneck. There is an increasing design complexity. Low power is important across markets — from smartphones to datacenters. Time to market remains critical as well. Feature-rich devices are growing the design size.

Timing closure schedule and complexity have been increasing. In fact, up until now, timing closure solutions are said to have not kept pace with design complexity. The number of timing views are increasing with each new process node. The increased margins make timing closure very difficult. Exponential growth in design size and complexity are stretching the analysis capacity. Time in signoff closure has been increasing up to 40 percent of the design flow at 20nm.

Come Tempus!
The Tempus timing signoff solution is big on performance, accuracy and closure. For performance, it facilitates massively parallelized computation, is scalable to 100s of CPUs and there are optimized data structures. It allows up to 10X faster path-based analysis (PBA) and advanced process modeling for accuracy. Finally, for closure, it provides up to 10X reduction in closure time, is placement and routing aware and offers unlimited MMMC capacity.

Tempus offers an unprecedented performance, and handles 100s of millions of cells flat! It has an innovative hierarchical/incremental analysis. For design closure, the multi-mode, multi-corner (MMMC) is distributed or concurrent. There is physically aware optimization, such as graph- or path-based. The PBA is a detailed view of timing based on slew propagation.

With Tempus, Cadence is solving the design complexity challenge by eliminating the signoff bottleneck and enabling customers to meet power, performance and time-to-market goals.

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