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Posts Tagged ‘Mentor Graphics’

IEF 2013: New markets and opportunities in sub-20nm era!

October 15, 2013 1 comment

Future Horizons hosted the 22nd Annual International Electronics Forum, in association with IDA Ireland, on Oct. 2-4, 2013, at Dublin, Blanchardstown, Ireland. The forum was titled ‘New Markets and Opportunities in the Sub-20nm Era: Business as Usual OR It’s Different This Time.” Here are excerpts from some of the sessions. Those desirous of finding out much more should contact Malcolm Penn, CEO, Future Horizons.

Liam BritnellLiam Britnell, European manager and Research Scientist, Bluestone Global Tech (BGT) Materials spoke on Beyond Graphene: Heterostructures and Other Two-Dimensional Materials.

The global interest in graphene research has facilitated our understanding of this rather unique material. However, the transition from the laboratory to factory has hit some challenging obstacles. In this talk I will review the current state of graphene research, focusing on the techniques which allow large scale production.

I will then discuss various aspects of our research which is based on more complex structures beyond graphene. Firstly, hexagonal boron nitride can be used as a thin dielectric material where electrons can tunnel through. Secondly, graphene-boron nitride stacks can be used as tunnelling transistor devices with promising characteristics. The same devices show interesting physics, for example, negative differential conductivity can be found at higher biases. Finally, graphene stacked with thin semiconducting layers which show promising results in photodetection.

I will conclude by speculating the fields where graphene may realistically find applications and discuss the role of the National Graphene Institute in commercializing graphene.

Jean-Rene Lequepeys, VP Silicon Components, CEA-Leti, spoke on  Advanced Semiconductor Technologies Enabling High-Performance Jean-Rene Lequepeysand Energy Efficient Computing.

The key challenge for future high-end computing chips is energy efficiency in addition to traditional challenges such as yield/cost, static power, data transfer. In 2020, in order to maintain at an acceptable level the overall power consumption of all the computing systems, a gain in term of power efficiency of 1000 will be required.

To reach this objective, we need to work not only at process and technology level, but to propose disruptive multi-processor SoC architecture and to make some major evolutions on software and on the development of
applications. Some key semiconductor technologies will definitely play a key role such as: low power CMOS technologies, 3D stacking, silicon photonics and embedded non-volatile memory.

To reach this goal, the involvement of semiconductor industries will be necessary and a new ecosystem has to be put in place for establishing stronger partnerships between the semiconductor industry (IDM, foundry), IP provider, EDA provider, design house, systems and software industries.

Andile NgcabaAndile Ngcaba, CEO, Convergence Partners, spoke on Semiconductor’s Power and Africa – An African Perspective.

This presentation looks at the development of the semiconductor and electronics industries from an African perspective, both globally and in Africa. Understanding the challenges that are associated with the wide scale adoption of new electronics in the African continent.

Electronics have taken over the world, and it is unthinkable in today’s modern life to operate without utilising some form of electronics on a daily basis. Similarly, in Africa the development and adoption of electronics and utilisation of semiconductors have grown exponentially. This growth on the African continent was due to the rapid uptake of mobile communications. However, this has placed in stark relief the challenges facing increased adoption of electronics in Africa, namely power consumption.

This background is central to the thesis that the industry needs to look at addressing the twin challenges of low powered and low cost devices. In Africa there are limits to the ability to frequently and consistently charge or keep electronics connected to a reliable electricity grid. Therefore, the current advances in electronics has resulted in the power industry being the biggest beneficiary of the growth in the adoption of electronics.

What needs to be done is for the industry to support and foster research on this subject in Africa, working as a global community. The challenge is creating electronics that meet these cost and power challenges. Importantly, the solution needs to be driven by the semiconductor industry not the power industry. Focus is to be placed on operating in an off-grid environment and building sustainable solutions to the continued challenge of the absence of reliable and available power.

It is my contention that Africa, as it has done with the mobile communications industry and adoption of LED lighting, will leapfrog in terms of developing and adopting low powered and cost effective electronics.

Jo De Boeck, senior VP and CTO, IMEC, discussed Game-Changing Technology Roadmaps For Lifescience. Jo De Boeck

Personalized, preventive, predictive and participatory healthcare is on the horizon. Many nano-electronics research groups have entered the quest for more efficient health care in their mission statement. Electronic systems are proposed to assist in ambulatory monitoring of socalled ‘markers’ for wellness and health.

New life science tools deliver the prospect of personal diagnostics and therapy in e.g., the cardiac, neurological and oncology field. Early diagnose, detailed and fast screening technology and companioning devices to deliver the evidence of therapy effectiveness could indeed stir a – desperately needed – healthcare revolution. This talk addresses the exciting trends in ‘PPPP’ health care and relates them to an innovation roadmap in process technology, electronic circuits and system concepts.
Read more…

Dr. Wally Rhines on global semiconductor industry trends for 2013


It is always a pleasure speaking with Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. I met him on the sidelines of the 13th Global Electronics Summit, held at the Chaminade Resort & Spa, Santa Cruz, USA.

Status of global EDA industry

Dr. Wally Rhines.

Dr. Wally Rhines.

First, I asked Dr. Rhines how the EDA industry was doing. Dr. Rhines said: “The global EDA industry has been doing pretty well. The results have been pretty good for 2012. In general, the EDA industry tends to follow the semiconductor R&D by at least 18 months.”

For the record, the electronic design automation (EDA) industry revenue increased 4.6 percent for Q4 2012 to $1,779.1 million, compared to $1,700.1 million in Q4 2011.

Every region, barring Japan, grew in 2012. The Asia Pacific rim grew the fastest – about 12.5 percent. The Americas was the second fastest region in terms of growth at 7.4 percent, and Europe grew at 6.8 percent. However, Japan decreased by 3 percent in 2012.

In 2012, the segments that have grown the fastest within the EDA industry include PCB design and IP, respectively. The front-end CAE (computer aided engineering) group grew faster than the backend CAE. By product category, CAE grew 9.8 percent. The overall growth for license and maintenance was 7 percent. Among the CAE areas, design entry grew 36 percent and emulation 24 percent, respectively.

DFM also grew 28 percent last year. Overall, PCB grew 7.6 percent, while PCB analysis was 25 percent. IP grew 12.6 percent, while the verification IP grew 60 percent. Formal verification and power analysis grew 16 percent each, respectively. “That’s actually a little faster than how semiconductor R&D is growing,” added Dr. Rhines.

Status of global semicon industry
On the fortunes of the global semiconductor industry. Dr. Rhines said: “The global semiconductor industry grew very slowly in 2012. Year 2013 should be better. Revenue was actually consolidated by a lot of consolidations in the wireless industry.”

According to him, smartphones should see further growth. “There are big investments in capacities in the 28nm segment. Folks will likely redesign their products over the next few years,” he said. “A lot of firms are waiting for FinFET to go to 20nm. People who need it for power reduction should benefit.”

“A lot of people are concerned about Japan. We believe that Japan can recover due to the Yen,” he added.
Read more…

Excerpts from Future Horizons’ IEF 2009 — II

November 1, 2009 Comments off

Presenting excerpts of some more key presentations made on day 1 and 2, resepectively, at the recently held International Electronics Forum 2009 (IEF 2009), in Geneva, Switzerland, from Sept. 30-Oct. 2, which was held under the auspices of the Geneva Chancellerie D’Etat & Istitut Carnot CEA LETI.

May I also take this opportunity to thank Malcolm Penn, chairman and CEO, Future Horizons.

“ICT: Key For Global Competitiveness” — Enrico Villa, chairman, CATRINE

Enrico heads up the Cluster for Application and Technology Research In Europe on NanoElectronics (CATRINE) and through his organisation Europe is preparing for our future with development projects in nanotechnology, microelectronics, photonics, biotechnology and advanced materials.

Electronic and information systems are worth $87 trillion and growing, which is about 10 percent of global GDP. Such systems have penetrated all aspects of life, created millions of jobs and has been a motor of productivity growth.

Microelectronics is a key enabling technology for electronics and ICT, and as a consequence the semiconductor market grows at twice this GDP. The role of electronics will increase in the future and will have an impact in society due to its use in healthcare, aids for an aging population, easing transportation bottlenecks and lowering energy costs.

To meet these targets electronics and ICT must be affordable to the population at large – meaning that semiconductors must meet the trend of doubling performance every two years, reduce price per function by 40 percent per year and aim for R&D nearly 20 percent of sales.

In an example given public lighting is 13 percent of energy costs – a change to semiconductor LEDs can save a third of this energy. Enrico sees moving from ideas to products is one area where Europe is weak, but thankfully projects Jessi/Eureka/Catrine/Medea+ are bringing together cooperation between European players.

This has enabled European companies and universities to work together and create critical masses to make global products. This is born out in the fact that Europe has several global-sized semiconductor companies and two European equipment-material suppliers that are world leaders.

“Raising The Bar On Semiconductor R&D Management, Execution & ROI” — Ronald Collett, CEO, Numetrics Management Systems

Working with the company PRTM Ron is tasked to raise the management competence within the semiconductor industry so companies can compete in the global arena. The semiconductor industry is going through a profound change with the vertically chip companies disintegrating and outsourcing their manufacture. Headcount has fallen, there are fewer start-ups and everybody is cutting costs.

Companies that will survive are those with well differentiated products and superior product development ability. PRTM has produced an integrated framework of product development capabilities, which compares company actual performance against industry best practice and timescales.

It is a fact that 60 percent of semiconductor projects slip in time by at least one quarter and 16 percent slip by more than one year. The system allows ‘fact-based planning and decision making’ and allows management to get no surprise shortfalls in revenue or margin.

At a detailed level, the engineer can make a fact-based project cost estimation and can reliably make staffing requirements and schedules. It allows ‘what-if’ project analyses and calculates risk. The immediate impact is usually a reduction of projects, but a better time-to-market and ROI. An industry shakeout is inevitable and demands will overwhelm all, but the best.

“Building Complex Embedded Software Applications On Leading Edge Silicon” — Martin Orrell, General Manager, Multimedia Technologies, The Technology Partnership

TTP is an independent product development company involved in a wide range of products including embedded systems in medical devices, PC peripherals, MP3 players and automotive, industrial and traffic control.

Martin’s view is that one of the difficulties in embedded design is to recognise that the hardware and software boundaries tend to blur. Using software rather than hardware has its advantages, particularly where the standards and specifications have not firmed up, but software often costs more than the customer planned.

Costs can be saved by the re-use of silicon and software IP, the starting platform and roadmap, trimming the specification and through innovation. TTP has a wide range of experience and can often view a customer project from a different perspective and Martin gave a number of good examples of case studies where this was the case.

To finalise, two tips were given to product developers: More complex software does not mean higher project costs and silicon targeted for a different market can enable innovative opportunities in your own market. Read more…

New routing tool likely to cover upcoming MCMM challenges: Hanns Windele, Mentor

April 17, 2009 Comments off

This is a continuation of the previous post based on the recent India visit of Hanns Windele, VP Europe and India, Mentor Graphics, where he met key industry figures in a session organized by the India Semiconductor Association. Windele is standing sixth from left, and Poornima Shenoy, president, ISA is standing fifth from right.

Multimode, multicorner tools
Windele mentioned that in every likelihood, another new routing tool would be coming in once the industry enters the 45nm/32nm space. “There is an increasing static timing analysis signoff complexity. The explosive growth in complexity requires multimode and multicorner tools,” he said.

Multicorner and multimode (MCMM) and manufacturing variability will drive the next generation place and route technology. Even in the low-growth markets, technical discontinuities create opportunities for market share changes. For instance, 65nm brings along more than 21 corners/modes scenarios; while 90nm has 10 corners, and 130nm only has four corners.

Therefore, another place and route tool will cover the upcoming MCMM problem. Even in low-growth markets, technical discontinuities create opportunities for market share changes.

Companies cannot afford the growing cost of EDA. Even the cost of design is growing exponentially, especially, verification, as well as embedded software development costs. Even the EDA revenue has been a flat 2 percent of the IC revenue. However, productivity has been growing as the number of engineers don’t seem to be multiplying in a great way. For example, the transistors produced per electronic engineer has been hearly four-orders of magnitude since 1985.

Showing optimism in recession
Turning to the ongoing recession, which has impacted the semiconductor industry, Windele said that 2009 will be most likely turn out to be the worst recession in the history of the global semiconductor industry.

“It seems to be heading that way. There is also a lot of reason for optimism. I feel that 2009 will be a lot milder than 1985 and 2001,” he said. Even the electronics indsutry’s growth rates have been slowing, decade by decade as well.

Therefore, with this ongoing global recession, why should we remain optimistic? Simple! A crisis translates into opportunities!!

Betting on India
No prizes for guessing where the most opportunities lie — India! Significantly, the ‘middle class’ in urban India becoming a majority. There is likely to be $3 trillion of discretionary spending by 2010. “People who can afford electronic and consumer goods will be growing further,” he added.

Windele cited ISA’s figures, which says that India’s electronics consumption is headed toward $300 billion by 2015. India’s electronic equipment consumption will likely grow at a CAGR of 30 percent through 2015. It was around $28 billion in 2005, and is likely to increase to $127 billion by 2010, and to $363 billion by 2015.

Yet another reason is the growing number of new cell phone subscribers in China and India, which will be 2x larger than the total US subscribers until 2011. Asia is, by far, the most attractive market for new cell phone sales. India will grow fastest, he added.

Downturns compared
Comparing the downturns of the recent years, Windele noted that 2008 and 2009 look different than the other downturns. “There is hardly any inventory left in the industry. One prediction is: as the price upswing comes, prices in the semicon industry will go up very quickly,” he noted.

Seeds already being sown for recovery in 2010. Already, the industry has experiecned two years of severe price declines in memory. Further, systems will be re-designed to take advantage of lower bit prices of FLASH and DRAM.

There will be consolidation and reduced investment in semiconductor capacity in 2008 and 2009. Ramp-up of new system designs will likely happen in 2010 during the period of reduced semiconductor supply.

Concluding, he added that Mentor Graphics became the number 1 EDA company in Europe as the company managed the crisis better than some of our competitors.

State of global semicon industry: Hanns Windele, Mentor

April 16, 2009 Comments off

During his recent trip to India, Hanns Windele, VP Europe and India, Mentor Graphics, took time off to meet key leaders from the Indian semiconductor industry over a session organized by the India Semiconductor Association (Windele is seen here admiring a memento presented by the ISA). He presented his observations of the global semiconductor industry.

According to him, the electronics industry is having a roller coaster ride today. “In the past, it was the same for everyone. Today, it is different! Those who have niche products are doing better than others. The economic crisis is accelerating the downturn in the semiconductor industry,” he added. Windele apprised the audience that the IC unit shipments had fallen 15 percent in Q408 (YoY).

Windele touched upon the various forecasts presented by various analysts (see chart). The common thing has been — all analysts have forecasted negative growth. The one key stand out has been Future Horizons, which otherwise remains optimistic, but this time forecast a deep negative growth in the industry.

Is the semicon industry really consolidating?
Given the downturn, is the global semiconductor industry really consolidating, as it should? Windele examined some significant revenue and rankings in an attempt to unravel this case. So, do the big keep getting bigger?

As per the semiconductor concentration of revenue, the No. 1 player has had less share in 2007 than in 1972. Applying the same yardstick with the top five companies, they too have had less share in 2007 than they have in 1972! Extending this to the top 10 companies indicated a similar picture!

This goes on to indicate that the global semiconductor industry has actually been “deconsolidating’ since the 1960s! Windele said that between 1965-72, 29 companies entered the market and captured share from the big companies.

Each decade seems to bring in more change. Also, new product families bring new opportunities. Consequently, leadership seems to be changing regularly as well. For instance, 2008 brought the first fabless company — Qualcomm — into the top 10!

Also, new fab-lite strategies are working as well, with companies such as Texas Instruments (TI), STMicroelectronics, Renesas, and Sony among the top 10 as per the H1-08 list.

Based on these assessments, Windele said that few companies have managed to stay on the top for more than three decades. The top 10 seems to be changing every decade, he added. The global semiconductor industry has definitely NOT been consolidating. The top fabs, however, have definitely been consolidating, but not the fabless! “You need to be with the right product at the right time at the right place, otherwise you’d disappear,” he cautioned.

Why hasn’t consolidation happened?
It would be interesting to note why the global semiconductor industry hasn’t been consolidating (yet)! According to Windele, this could be due to:

* Unlike trends in steel, chemicals and automobiles, etc., the electronics industry achieves a reduction in cost per transistor of about 35 percent per year, every year.
* This change enables totally new applications addressing totally new markets.
* These new applications and markets are driven by innovators that are frequently new entrants into the electronics industry.

Opportunities for change
Once the EDA market stabilizes, would there be opportunities for change? There should be plenty of opportunities!

The place and route market has definitely not been growing. Rather, it has been a flat market over the past several years. Nevertheless, new EDA startups lead each new generation of place and route technology. According to Windele, there will be another new routing tool coming in once the industry enters the 45nm/32nm space.

Part II of this post continues in the next blog post.

Mentor Graphics: DFM is where all the value is!

September 28, 2008 Comments off

As promised, here is the concluding part of my discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

We went over the design for manufacturing (DFM) challenges and how yield can be improved. He also touched upon the design challenges in 45nm and 32nm, respectively.

Given that the semiconductor industry does speak a lot about DFM, what steps are being taken to improve on the overall yield?

According to Sawicki, in the VLSI microchip era, yields started at 60-70 percent, and so DFM wasn’t required. However, in the nanochip era, DFM is where all the value is. [VLSI Research.]

Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor GraphicsHe added that at smaller geometries, manufacturing variability has a much greater impact on timing, power dissipation, and signal integrity. Traditional guardbanding is no longer sufficient to guarantee competitive performance at acceptable yields, and excessive design margins erase the advantages sought by going to the next node in the first place.

Moving to advanced technologies without dealing effectively with manufacturing variability can actually put a design at a competitive disadvantage due to low parametric yield.

“Successful IC implementation requires a detailed understanding of how variability affects both functional and parametric yield. Customers need a manufacturing-aware engineering approach that extends across the entire physical implementation life cycle, starting with cell library development and extending through place and route, physical verification, layout optimization, mask preparation, testing, and failure analysis.

“They need a design flow that helps them “co-optimize” for both performance and yield simultaneously, based on accurate models of manufacturing process variability. The ability to do this quickly and effectively can give IC designers a powerful competitive advantage,” Sawicki said.

There is no silver bullet! It takes a broad-based, well-integrated approach to have a significant and consistent impact on manufacturability.

According to him, Mentor Graphics provides a complete manufacturing-aware design-to-silicon solution addressing random particle effects, small-scale device and interconnect interactions, lithographic distortions and process window variations, and thickness variations resulting from chemical-mechanical polishing (CMP) and variable film deposition and etch rates.

“Our tools incorporate comprehensive, highly-accurate models that have been tuned and verified for specific manufacturing environments, and address every stage of the digital IC implementation life cycle,” he added.

So, how is Mentor handling 45nm and 32nm design challenges?

Sawicki added: “Advanced process nodes present challenges at every stage of IC implementation, from place-and-route, through physical verification, layout enhancement, testing and yield analysis. Mentor has a complete design-to-silicon flow that addresses the critical challenges of IC implementation at every stage.”

Mentor on EDA trends and solar/PV

September 24, 2008 Comments off

This is a continuation of my recent discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

There have been whispers that the EDA industry has been presently lagging behind semiconductors and is in the catch-up mode. “That’s a matter of perspective. There are definitely unsolved challenges at 32nm and 22nm, but the reality is that we are still in the technology development stage,” he says.

For EDA tools that address implementation and manufacturing issues (i.e., Mentor design-to-silicon products), there are dependencies that cannot be fully resolved until the process technology has stabilized. Mentor Graphics is laying the groundwork for those challenges and working in concert with the process technology leaders to ensure that our products address all issues and are production-worthy before the process technology goes mainstream.

On the other hand, although Mentor’s products are fully-qualified for 45nm, there have only been a handful of tapeouts at that node, so for the majority of customers, we are ahead of the curve.

On ESL and DFM as growth drivers
ESL and DFM are said to be the new growth drivers. Sawicki adds: “As Wally Rhines has said in his public presentations, system level design and IC implementation are the stages of development where there are the most challenges, and therefore the most opportunities. To continue the traditional grow spiral that the electronic industry has enjoyed as a result of device scaling, we need more sophisticated EDA solutions to deal with both of these challenges.”

ESL is responding to the growth of design complexity and the need for earlier and more thorough design verification, including low power characteristics, and software integration.

The Design-to-Silicon division is addressing the issues of IC implementation which result not only from the increase in design complexity and devices sizes, but also from increasing sensitivity of the manufacturing process to physical design decisions, a phenomenon often referred to as “manufacturing variability.”

Although the term “Design-For-Manufacturing” reflects the need to consider manufacturability in design and to optimize for both functional and parametric yield, it is important to emphasize that DFM is not simply an additional tool or discrete step in the design process, but rather an integration of manufacturing process information throughout the IC implementation flow.

With single threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out. It would be interesting to see how is Mentor handling this.

According to Sawicki, Mentor has incorporated sophisticated multi-threading and multi-processing technologies into all of its performance-sensitive applications, from place-and-route, through physical verification, resolution enhancement and testing.

He says, “Our tools have a track record of impressive and consistent and performance and scalability improvements, which is why we continue to lead the industry in performance.”

In addition to merely adding multi-threading and support for multi-core processors, Calibre products have a robust workflow management environment that automatically distributes the processing workload in the most efficient manner across any number of available clustered computing nodes.

Mentor’s Olympus-SoC place-and-route is inherently scalable due to its advanced architecture which includes an extremely efficient graph representation for timing information, and a very concise memory footprint. In addition, all the engines within Olympus-SoC can take advantage of multi-threaded and multi-core processors for high performance. These features enable Olympus-SoC to handle 100M+ gates designs in flat mode without excessive turnaround time.

Mentor’s ATPG tools are also designed to operate in multiprocessing mode over the multiple computing platforms to reduce test pattern generation time. In addition, Mentor test pattern compression technology reduces test pattern volume and test time, making it feasible to fully test 100M gate devices and maintain product quality without an explosion in test cost.

With EDA is starting to move up to the system level, will this make EDA less dependent on the semiconductor world?

Sawicki agrees that there are challenges at both the front end and back end of the electronic products design and manufacturing life cycle. Both of these opportunities are growing. In addition, developments like multi-level (3D) die packaging, through-silicon via (TSV) structures and other non-traditional techniques for device scaling are pushing system and silicon design issues closer together.

Reaching the 22nm node will require highly compute intensive EDA techniques for physical design to compensate for limitations in the manufacturing process. Beyond that, we could see a major shift to new materials and manufacturing techniques that would open new green fields for EDA in the IC implementation flow.

EDA going forward
How does Mentor see the EDA industry evolving, going forward?

Sawicki adds: “There are three key trends to watch. Firstly, for design to remain affordable at the leading edge, we need to enable radical increases in productivity. Electronic System Level (ESL) design is the key here, allowing designers to move to a new level of abstraction for both design and verification.

“Secondly, the challenges of manufacturing a well-yielding and reliable device as we move to 22nm will require a far more sophisticated physical implementation environment—one that accounts for physical effects in the design loop, and accounts for manufacturing variability in it’s optimization routines.

“Finally, the manufacturing challenges also open significant opportunity for EDA in the manufacturing space. A great example of this is the September 17, 2008 announcement we did with IBM on a joint development program to enable manufacturing at the 22nm node.”

Finally, given the roles already defined by Magma and Synopsys in solar, is there an opportunity for EDA in solar/PV?

According to Sawicki, as the photovoltaic devices have very simple and regular structures, most of the opportunity for EDA is not in logic design tools, but in material science, transistor-level device modeling, and manufacturing efficiencies with a focus on conversion efficiency and manufacturing cost reduction.

EDA’s role in solar will be in the newer areas related to Design-for-Manufacturing and other manufacturing optimizations, he concludes.

Our last discussion on DFM will follow in a later blog post!

Despite EDA challenges, Mentor keeps faith on India

September 21, 2008 Comments off

Great! All of these EDA firms, despite their current financial woes, remain strong and bullish on India! Mentor Graphics is no exception in this case!

It is well documented that the global EDA industry, along with the global semiconductor industry, has not had a smooth ride this year. However, this situation has only made both the industries work harder toward restoring some recovery.

Thanks to Veeresh Shetty, a dear friend, and Marcom Manager-Pacrim South, Mentor Graphics, I had the pleasure of meeting up with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics Corp., during the recently held EDA Tech Forum in Bangalore.

We discussed a range of issues, such as the state of the EDA industry, Mentor’s focus on India, and low-power design challenges. I did not discuss the proposed acquisition of Mentor by Cadence, as I feel it is no point in going over what was never on the cards, at least, for now.

According to Sawicki, Mentor Graphics is very optimistic about semiconductors and electronics, especially in India. “The EDA industry is currently having a pretty challenging environment. The recession in 2002 was the deepest in its history,” he says.

“We (the EDA industry) haven’t had the growth rates we would like. However, we have done better. We have re-invented Mentor,” adds Sawicki. “We have now invested more in back-and-route ICs, which is about 40 percent of our revenue. Our product portfolio is the youngest within the company.” He adds that the recession has been more in semiconductors. However, take out memory, and the scenario changes.

The drive of the semiconductor industry toward smaller and smaller features sizes requires more sophisticated correction methods to guarantee the final tolerances for the etched features in both wafer manufacturing and mask making.

Flat growth likely for EDA
Commenting on EDA industry’s growth, Sawicki, adds that growth will be flat in 2008. Interestingly, the growth rate for EDA was 10 percent during the last two years. He notes: “EDA always does best when it delivers new technology. There are two reasons. One, on the manufacturing side of things. The extra results will be completely delivered by the software.”

The other reason is that the aspects of manufacturing power and manageability will assume great importance. “Finally, the ESL space also provides the potential for growth. It also brings out a whole new design capability,” he notes.

Given the global semiconductor scenario, Mentor is also looking at other markets outside semiconductors, especially automotive. Sawicki adds that this quarter, 20 percent of Mentor’s business has been from the automotive segment.

There have been several global initiatives aimed at consolidation in the recent past. Sawicki says: “Consolidation should not be looked at as a goal. We also do acquisitions in the technology space. It augments a strong position.”

So what are some of the other challenges facing the industry? Sawicki lists those as the economics of the industry itself, especially the design and verification costs.

On low power design, Sawicki agrees that there has been a transition of electronics from the US to Asia. “You have got to handle far lower power downward. We can reduce leakage current by 20-30 percent. Looking forward, how do you tie in ESL with physical design? When doing ESL, you can do architectural exploration. I will have my ESL to drive the place-and-route tool. I can get fast execution as well as low leakage power.”

He advises that India has the ability to go beyond the innovation that has been happening.

Mentor in India
Mentor Graphics has three sites in India. It has R&D centers in Hyderabad and Noida, near New Delhi, and a sales and support office in Bangalore. The Hyderabad R&D center handles system design, while the Noida R&D center takes care of the front-end side, such as functional verification products.

Raghu Panicker, sales director, India, Mentor Graphics, says that the company has been very bullish on India. “We do not see any lull anywhere. Lot of design starts are happening here, in India,” he adds.

I will continue my conversation with Joseph Sawicki in the next blog!

EVE betting strong on Indian semicon industry

August 10, 2008 Comments off

I have known Montu Makadia, Director and Country Sales Manager, EVE Design Automation Pvt. Ltd, since his days at eInfochips. It was interesting to learn more about the company and its strategy for India over the coming years.

For those who came in late, EVE offers a broad range of hardware-assisted verification solutions on the market, from acceleration to fast emulation and prototyping, with the most cycles per dollar. EVE products lead to a significant shortening of the overall verification cycle of complex integrated circuits and electronic systems design.

EVE products also work in conjunction with popular Verilog and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics. Its sales headquarters in the United States is in San Jose, California. EVE’s manufacturing, R&D and corporate headquarters is located in Palaiseau, France.

Estimating the Indian semiconductor industry, Makadia said the global semiconductor market continues to grow, driven by the demand for consumer-oriented electronic devices. The Indian semiconductor industry, in particular, appears quite strong and is an attractive market opportunity for EVE.

“That’s because of its push into digital media, telecom and mobile communications markets that presents tremendous growth opportunities for companies such as EVE,” he said.

According to him, industry watchers should see strong growth in semiconductors in India in the coming years, propelled by smaller process technologies, multi-core architectures and the ever-increasing software content in system-on-chips (SoCs). With more SoC designs, the demand increases for hardware/software co-verification solutions.

EVE’s belief in the Indian market has been so strong that EVE Design Automation Pvt. Ltd., a wholly owned subsidiary based in Bangalore, was formed in 2007. EVE DA markets and supports the Zebu (for ‘zero bugs’) hardware-assisted verification platforms of accelerators, emulators and FPGA prototypes.

ZeBu enhances SoC performance
So, how exactly does ZeBu help analyze, benchmark and measure performance of the system-on-chip (SoC) over realistic scenarios?

Makadia said: “We have been really successful last year promoting the Zebu based emulation platform. Our existing customers, as well as new prospects in India, have shown great interest and recognized real value in adopting Zebu, not only for hardware verification but also for hardware and software co-verification.

“The Zebu platforms enable software validation and co-verification in a range of several megahertz, thus replacing the deployment of ASIC or prototype boards. For instance, we booted operating systems, e.g., Linux and WinCE, on processors designs mapped into ZeBu emulation platforms at 10-20 megahertz using a transactor-based verification methodology.”

How can EVE’s ZeBu be the choice of startups who need first-pass silicon success? Makadia added that startups in need of first-pass silicon success and designers worldwide have found that emulation tools such as Zebu are the only option for debugging hardware and testing the integration of hardware and software within complex SoCs.

He noted: “This is especially true when the task calls for executing billions of cycles in less than one hour and there’s a need for full visibility into the hardware. The ability to track hardware and software interaction offered by Zebu is considered a plus.”

ZeBu helps to analyze benchmark and measure SoC performance with realistic scenarios by running at speeds well above one megahertz. It is capable of executing complete test scenarios within an acceptable timeframe and just shy of running in real time.

This is interesting, and further examination needs to be done to evaluate how the emulation segment is performing and where it is evolving, especially, in India?

Makadia said: “After several years of stagnation, the overall market for emulation has been growing due to escalating complexity in hardware and in embedded software. Other factors have made emulators attractive once again. They run faster, are easier to use, have smaller footprints and are cheaper than older generations.”

The growth trend for emulation and hardware/software co-verification solutions will continue in the foreseeable future, especially in India.

Speaking on EVE’s overall strategy, he added that the company will continue to introduce even better performing emulation platforms through innovative architectures and enhanced supporting software to increase adoption by all market segments of the electronics industry.

Further, EVE is evaluating strategic partnerships and possible mergers with various synergistic companies to expand the attraction of its offerings.

EDA as DNA of growth

June 18, 2008 Comments off

The EDA industry today is abuzz with the proposed takeover bid by Cadence Design Systems for Mentor Graphics, and the reported rejection of that bid by Mentor.

This is a consolidation within the EDA industry waiting to happen. My gut feeling is that it will happen, though it may take some more time.

Those in the semiconductor space are well aware of the role EDA plays as far as chip designing is concerned. With India’s growing might in semiconductors, the EDA companies in India are witnessing consumption rising than ever before.

I recently happened to get into a discussion with Rahul Arya, Marketing Director, Cadence Design Systems (I) Pvt. Ltd, on how the industry has been performing, and how are the EDA companies addressing the design challenges, a few days before the Cadence-Mentor story surfaced.

Following the semiconductor industry trends, the consumption of EDA technologies is growing in regions outside of the US and Europe. According to Arya, the size of the EDA market worldwide is estimated to be about US $5 billion today.

The top three EDA companies — Cadence, Mentor and Synopsys — command three-quarters share of the entire EDA market worldwide. Imagine, what it would do to the EDA industry and to Cadence, if Cadence were to take over Mentor!

EDA in India
Coming to the status of the EDA industry in India, it is a pretty good reflection of what’s happening worldwide. The industry in India is growing and it is healthy. As per the ISA F&S Report 2005, the EDA market in India was estimated at US$110m.

The reasons for this growth are multiple. For instance, Cadence’s customers are growing and hence, so is Cadence. “With all of the major semiconductor MNCs having expanded their footprints by setting up India design centers, more EDA software is getting consumed in India. Indian design services are also growing. Also, some startups are coming up, like Cosmic Circuits, Sankalp, etc., and they are gaining momentum,” added Arya.

So how exactly are the EDA companies addressing 45nm (and 32nm) design challenges? If you look at the work being done in India, it is now pretty cutting edge, and very comparable to the rest of the world.

Arya added: “Our customers are looking for the 3Cs — complexity, cost and convergence. The end users are asking for more features. For example, in their mobile or any other electronic device, which is driving our customers to pack in more functionality on the chips.

“Our customers have multiple challenges at 45nm and below, notably low power, analog-mixed signal and Design for Manufacturing (DFM).”

Challenges in 45nm and below
And what are those? As the industry pushes toward smaller process geometries, the existing design infrastructure must be upgraded holistically to automate power-lowering design techniques. Most power-control methods in use today are manual and implemented ad hoc, leading to an increased risk and cost.

Across the design and manufacturing chain, an urgent need has emerged for an automated, power-aware design infrastructure. To facilitate and support a new era of low-power design innovation, Cadence has formed the Power Forward Initiative (PFI).

Drawing from the collective expertise of leading technology companies, the Power Forward Initiative will create a more systematic, integrated approach to low-power design, providing a platform for higher-level exploration and IP re-use.

The PFI members are already at work on validating the Common Power Format (CPF), a new open specification language that captures all power-specific design, constraint, and functionality requirements, such as multi-supply voltage and power shutoff, in a single file.

Arya noted: “By linking design, verification, and implementation domains, the Common Power Format enables automation of power-reduction techniques and increases predictability. No longer constrained by the risk of low yield or costly re-spins, design teams can focus their time and resources on what matters most —- innovation. Achieving both functional and structural verification before incurring manufacturing costs, and with greater time-to-market opportunities, companies across the design and manufacturing chain can adopt new process geometries and start low-power design projects profitably.

On the subject of DFM, EDA companies are trying their utmost to improve yield. Cadence is trying to bring lot of analysis early in the cycle. The designer has more visibility on those effects, before they get manufactured. It has a host of technology offerings to enable the designers make early decisions.

For example, Cadence has recently worked with TSMC on 9.0 reference flow. It has also worked with ARM on a low-power methodology. The idea is that an industry-wide collaboration will ensure that EDA companies like Cadence are able to provide value to customers.

As customers grapple with technology and time-to-market challenges, the EDA industry will be the DNA of growth.

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