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Moore’s Law could come to an end within next decade: POET

August 28, 2013 1 comment

Dr. Geoff Taylor

Dr. Geoff Taylor

POET Technologies Inc., based in Storrs Mansfield, Connecticut, USA, and formerly, OPEL Technologies Inc., is the developer of an integrated circuit platform that will power the next wave of innovation in integrated circuits, by combining electronics and optics onto a single chip for massive improvements in size, power, speed and cost.

POET’s current IP portfolio includes more than 34 patents and seven pending. POET’s core principles have been in development by director and chief scientist, Dr. Geoff Taylor, and his team at the University of Connecticut for the past 18 years, and are now nearing readiness for commercialization opportunities. It recently managed to successfully integrate optics and electronics onto one monolithic chip.

Elaborating, Dr. Geoff Taylor, said: “POET stands for Planar Opto Electronic Technology. The POET platform is a patented semiconductor fabrication process, which provides integrated circuit devices containing both electronic and optical elements on a single chip. This has significant advantages over today’s solutions in terms of density, reliability and power, at a lower cost.

“POET removes the need for retooling, while providing lower costs, power savings and increased reliability. For example, an optoelectronic device using POET technology can achieve estimated cost savings back to the manufacturer of 80 percent compared to the hybrid silicon devices that are widely used today.

“The POET platform is a flexible one that can be applied to virtually any market, including memory, digital/mobile, sensor/laser and electro-optical, among many others. The platform uses two compounds – gallium and arsenide – that will allow semiconductor manufacturers to make microchips that are faster and more energy efficient than current silicon devices, and less expensive to produce.

“The core POET research and development team has spent more than 20 years on components of the platform, including 32 patents (and six patents pending).”

Moore’s Law to end next decade?
Is silicon dead and how much more there is to Moore’s Law?

According to Dr. Taylor, POET Technologies’ view is that Moore’s Law could come to an end within the next decade, particularly as semiconductor companies have recently highlighted difficulties in transitioning to the next generation of chipsets, or can only see two to three generations ahead.

Transistor density and its impact on product cost has been the traditional guideline for advancing computer technology because density has been accomplished by device shrinkage translating to performance improvement. Moore’s Law begins to fail when performance improvement translates less and less to device shrinkage – and this is occurring now at an increasing rate.

He added: “For POET Technologies, however, the question to answer is not when Moore’s Law will end – but what next. Rather than focus on how many more years we can expect Moore’s Law to last – or pinpoint a specific stumbling block to achieving the next generation of chipsets, POET looks at the opportunities for new developments and solutions to continue advancements in computing.

“So, for POET Technologies, we’re focusing less on existing integrated circuit materials and processes and more towards a different track with significant future runway. Our platform is a patented semiconductor fabrication process, which concentrates on delivering increases in performance at lower cost – and meets ongoing consumer appetites for faster, smaller and more power efficient computing.”
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Top 10 technology predictions for 2009: Deloitte

March 28, 2009 Comments off

Deloitte recently came out with its TMT (telecom, media and technology) predictions for 2009. Here are some bits from the technology predictions for 2009. May I take this opportunity to thank V. Srikumar, partner, Deloitte Haskins & Sells, for sharing this study.

1. Making every electron count: the rise of the SmartGrid.
Major manufacturers and utilities should explore partnerships with, and consider acquisitions of smart energy companies, advises Deloitte. SmartGrid technologies have the potential to reduce up to 30 percent of electricity consumption and dramatically reduce the need to construct new power plants or operate environmentally harmful sources of generation. They also bring computer intelligence and networking to the electrical network. SmartGrid also allows for more efficient use of the existing infrastructure. Is there room for nuclear power? Possibly, yes!

2. Gadgets for free* (*subject to contract)
According to Deloitte, bundling products and services together may prove essential in 2009 to stimulate an otherwise nervous, stalled market. This approach may well become pervasive in 2009, and likely be extended to a wide range of devices, including TV (bundled with subscriptions), music equipment (bundled with music), and high-end computers (bundled with everything — from technical support to remote back-up services).

3. Disrupting the PC: the rise of the netbook.
Even since the introduction of the Intel Atom processos, netbooks and mobile Internet devices have gained momentum — at least, in print and web. Sony’s pocket device only adds to the glamour. According to Deloitte, the appeal of netbooks has been categorized as making ‘great second computers for normal people, third computers for techies, and the first computer for children.’ Even carriers should consider adding netbook subsidies into their current cash-flow estimates. They should also analyze the impact of wireless data usage on their networks — driven by netbooks.

4. Moore’s Law and risk.
A corollary to the famous law is applied to the falling prices for digital storage and the rise in the types and speeds of communication networks. However, these have combined to add to the corresponding risk associated with information leakage and data theft. Even a small memory stick can hold volumes of data! Companies could probably never realize that their data has gone missing or that intruders were regularly accessing their networks. Loss of analog data and need to secure analog copies should not be overlooked as well.

5. The common sense of green and lean IT.
Green IT, perhaps, the most misused IT term of this year and the past! Nevertheless, the Deloitte study, in 2009, the aggregate volume of the world’s data centers is likely to continue to grow, albeit possibly at a slower pace than in previous years. The efficiency of data centers is, however, likely to vary considerably. The latest, purpose-built data-centers should attain a power-unit effectiveness (PUE) rating of 1.2 or better. A typical enterprise data-center is likely to achieve a PUE of 2.0 or worse. Energy consumption for IT should be linked to the overall approach to energy for a company. All departments can have a role to play in making technology more efficient, by applying some common sense.

6. Downsizing the digital attic.
The ever growing danger of digital storage is the fact that users continue to assume that storage space is infinite (just as we do with our possessions). Companies should assess whether their total cost of storage is growing faster than revenues, and if so, whether this is beneficial to them and enterprises should review all aspects of digital data use and management, advises Deloitte. An option could be off-site storage. However, companies would also need to monitor both costs and regulatory implications.

7. Generic becomes the ‘IT’ brand.
In 2009, we could well find companies and consumers actively seeking out unbranded or relatively unknown technology brands on the basis that they are good enough and, more importantly, significantly cheaper! For the established brands, dropping prices may increase sales in the short-term, but might cheapen a brand’s image in the long term. How good would these alternative suppliers be? Deloitte feels that using alternative suppliers is likely to require users to become familiar with a new interface, perhaps causing a drag on productivity. Enterprises should look at approaches of minimizing this disruption, for example through the use of digital skins that mimic interfaces and appearances that users are more familiar with.

8. The digital ambulance chaser gets supercharged.
According to Deloitte, digital litigation may prove recession proof, or even counter-cyclical, in 2009. All companies involved with digital products and services should be wary of unwittingly being caught out by the legislation related to digital infractions — whether committed against a consumer, an employee, an acquisition, a partner or another business. Even technology companies should constantly monitor how consumers actually use their digital products and services and whether this may create legal issues, advises Deloitte.

9. Social networks in the enterprise: Facebook for the Fortune 500.
Again, on social networks and the enterprise. According to Deloitte, it seems as though 2009 could be the breakout year for social networks in the enterprise. Internal and external spending on social networking solutions from IT providers and carriers may approach $500 million. Social networks are likely to be considered an inexpensive solution in what is likely to be a financially constrained IT spending environment. Perhaps, telcos and IT solutions providers also need to invest in ESN and develop the expertise and credibility to deploy these solutions if or when they become more broadly adopted, and start becoming a more significant source of revenues.

10. Sinners become saints.
This is an interesting observation, where Deloitte looks at genetically modified (GM) foods. The need to feed people, coupled with the need to conserve water, is likely to prompt a re-evaluation of GM foods. Nevertheless, it advises that governments should take a lead on investigating, understanding and communicating the various solutions available for addressing the world’s key sustainability challenges. “In 2009 it may even be considered virtuous to create dishes comprising GM ingredients, packaged in plastic, in kitchens powered by nuclear fuel,” adds Deloitte.

FPGAs have adopted Moore’s Law more closely!

November 3, 2008 Comments off

How true! Field programmable gate arrays or FPGAs have become faster, denser and more complex over the years!

Speaking at the recently held Altera SOPC conference, S. Janakiraman, President and CEO-R&D Services, MindTree, and former chairman, India Semiconductor Association (ISA), said these had found acceptance in a wide range of market segments. “FPGAs are everywhere, be it telecom or industrial or medical,” he added.

Once relegated to simple glue logic design, FPGAs are challenging SoCs today. The million-gate FPGAs are, in fact, quite common. What’s more, ASSP like features, for example, PCI Express, USB, etc., have also found their way into FPGAs.

FPGAs have adopted Moore’s Law more closely than any other device technology! They even ‘help’ in ‘ratifying’ new process nodes.

Janakiraman said: “With the ever increasing costs of designs and declining ASIC starts, FPGAs offer a considerably less riskier approach, development costs, tools and testing – even at latest technology nodes.”

So what would be the factors driving change? These are multiple, and actually split into cost, performance, time-to-market and also field-upgradeable hardware.

From the cost aspect, functions in a system with standard ICs are performed by dedicated discrete components on a PCB. The FPGA route can reduce routing congestion and lower costs by enabling the use of smaller boards with less layers and lower component count.

Next comes performance, and a key factor in accelerating performance is parallel implementation. Here too the FPGA can be easily programmed to handle the same sequential instruction set by leveraging multiple micro-CPUs, connected by very wide internal buses.

Time-to-market has obviously become critical with the consumerization of electronics. As a result, the FPGAs are increasingly entering this segment because of the obvious advantages of early product introductions.

As for the field upgradeable hardware, Janakiraman elucidated an example: configuring video capture card for Europe (PAL), NA (NTSC), JAPAN (SECAM), need one hardware configuration with an FPGA on it. Depending on the location end-user downloads country specific driver that configures FPGA accordingly.

Jani Sir, as he is affectionately known, delivered the keynote at the Altera SOPC, which really touched upon how a fabless India was shining.

I also managed to catch up with Jordan Plofsky Senior Vice President Market, Altera. All I can add here as a sneak peek is: uncertainty favors FPGA’s usage! Let’s see how true — in my next blog!

Semicon to grow 12pc in 2008: Future Horizons

May 14, 2008 Comments off

If there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm!

According to Malcom Penn, CEO, Future Horizons, we are dealing with a semiconductor industry in ‘deep trauma.’ He was delivering the company’s forecast at the recently held International Electronics Forum (IEF) 2008 in Dubai, predicting a 12 percent growth this year despite signs of a wobbling US economy.

Is there a need to get back to the industry basics? “Semiconductors are a peculiar business; the only sane strategy is to bet the company regularly,” once remarked Dr Gordon Moore.

Penn noted that the current industry status is somewhat confused and uncertain. Short-term issues are dominating the agenda.

Longer-term structural trends are unclear. The traditional IDMs are currently going through a mid-life ‘new business model’ identity crisis, and the start-ups are struggling to even reach critical mass! And all of this has been happening amidst intense economic uncertainty

“Now is the time for strong nerves and determination,” Penn said. According to him, the underlying industry fundamentals are sound and there is no end in sight to the ‘make-lunch-or-be-lunch’ ethos.

The emerging economies like India and China have so far been less affected by the financial market’s turbulence. In fact, the emerging and developing economies were shifting the global growth dynamics.

Chip industry in best possible shape
A forecast health warning is: IF the global economy collapses, it will take the chip market with it. However, Future Horizons feels that if there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm.

The ASPs are an enigma wrapped up in riddle. The course of ASPs (like love) never runs smooth. Wobbles happen! ASPs are also the perennial (and least understood) industry wild card. ASPs are generally driven by new IC designs, and that takes time (sometimes three to four years). Post-2001, value recovery lost one generation (130nm impact). The ASP recovery ‘wobbled’ in 2007 (memory and MPU price wars). Barring a recession, Future Horizons forecasts that ASPs will recover in 2008 (it has already started).

12 percent growth likely
Future Horizons’ 2008 forecast summary and assumptions (as of May 2008) are — ‘12 percent’ growth — ’10 percent’ units / ‘2 percent’ ASP. There may be no global economic recession, although US/UK/Eurozone might wobble — which they are! No significant inventory correction will probably take place, but there are always Q4>Q1 adjustments, and there’s nothing special about that either.

There could be lower fab capacity expansion due to 2007/2008 capex slowdown, which is inevitable and irreversible. There is also a possibility of a more stable memory price erosion — which means, back to the learning vs. bleeding curve, and prices have since hardened. If the global economy holds, the 2H-08 growth will likely be strong. This, if the capacity, ASP and units are all pulling together, which is said to be happening.

Therefore, Penn feels it is too early to call for a (major) downward revision. Q1 08 was a lot stronger than conventional wisdom feared.

“That’s the rational analysis, but semiconductors aren’t rational. It could just as easily be another single digit growth year,” Penn added.

Danger signs to watch out for
So, what are the danger signs one should watch out for? These would be capacity — it is hard to see how this can spoil 2008, provided unit growth holds up, but there is a need to watch capex. Another factor is demand — the current IC unit demand is sustainable provided the economy holds up, so there is a need to watch the inventory.

Next comes the economy! The current outlook continues to be uncertain with risks all on the downside. ASPs are the key to recovery, but always the first line of defence. ASPs could still derail 2008, but the trends are encouraging.

What’s driving the market?
In semiconductor 7.0 — or the 7th decade of the transistor revolution, the same things, as always, are driving the market. These are: technology, legislation — energy saving/conservation and structural — the relentless analog to digital conversion. All of these are combining to do what the chip industry does best — enabling something that was previously impossible. Penn contends, “This industry has nowhere near run out of steam!”

New applications continue to drive the market, with automotive, industrial and medical, mobile phones, and PCs and servers, dominating. The PC market is dominating, but going nowhere fast. Mobile phones have become more interesting, but have conflicting priorities. The challenges are: how to protect the existing cost structure and subscriber base and how to add useful and affordable value-add services! Evidently, “chipset suppliers love the high end, market loves the low end.”

There is definitely an increasing automotive semiconductor content. A solid annual growth has been prediced (CAGR 2006-11) for vehicles — 5.5 percent, systems — 11.5 percent, and semiconductors — 13.3 percent. Some other new areas are motor control and energy, as well as lighting and photovoltaic, besides medical electronics. Robotics is yet another interesting area.

Key industry issues
It is clear that more chips per wafer equals less cost per chip and more transistors per die equals more functionality. Several billion transistors gives phenomenal design flexibility as well. Considering total ICs and MOS ICs, in the MOS capacity build out by technology node, there has been no change in volume ramp profile despite the hype.

As for the evolution of the technology node, definitely, 45nm is a revolutionary step from 65nm. In all likelihood, 32nm will be a natural evolutionary. However, Penn cautioned that 22nm would be another ‘difficult’ transition!

There is no doubt that 65nm will be tomorrow’s leading-edge workhorse, having the same basic Si gate/SiO2/MOSFET structure. Nevertheless, 45nm will herald a totally different structure — metal gate/high-k/thin FET/deep trench design, etc. Also, 45nm will herald a new way of system design.

Is fabless right?
Is Fablite a valid option? While there is nothing wrong with being fabless, people are just not sure whether the best starting point is being an IDM. Teamwork has to be perfectly orchestrated as competition is tough.

As for the market share dynamics, the top 10 companies (IDMs) have been losing share. Fabless share has been growing, but it is still relatively small.

Coming to the realities of the foundry market, TSMC’s lead is now unassailable. Were it an IDM, it would be No. 2, challenging Intel and passing Samsung. Moving more into design looks inevitable.

Finally, execution, and not technology, is everything! Execution has and will continue to make the difference. Applications (software) will play the role of the key differentiator as well, and it has value. Design is the means to an end, and not the end.

From the chip industry’s perspective, the electronics market was traditionally Japan, North America and Western Europe. It now encompasses the entire Asian rim, China, Eastern Europe and India. Far from maturing, the chip industry itself is still in its volatile, high-growth phase, with at least a further 20 years of strong growth in prospect. Penn said, “The underlying growth drivers for chips has never been better.”

Back to basics
We started with the need to get back to industry basics. We end in the same way! Stick to basics like:

* Don’t invest in low cost areas just because they are cheap — they have a habit of becoming high cost tomorrow, plus the hidden extras.
* Don’t make outsourcing decisions just because they are easy — especially if there’s no way back.
* Don’t make strategic cut-backs just to trim the bottom line — some decisions, e.g., R&D, take a long time to impact, then it’s too late.
* Stop looking for high volume/high value market niches — they don’t exist, need to learn how to compete
* Do show strong leadership
* Do have a long-term plan and stick with it — even if it negatively impacts ‘the next quarter’ balance sheet
* Do show a commitment and determination to succeed
* Do stay focused and resistant to external meddling
* Do execute ruthlessly — this is the key competitive differentiator)
* Do … just do it with passion — it’s the passion that makes the difference

R&D innovation: nano-scale to tera-scale

January 29, 2008 Comments off

Justin Rattner, VP and Senior Fellow CTO, Intel Corp., while speaking at the recently held CXO Forum organized by the India Semiconductor Association (ISA), highlighted the various innovations Intel has created over the years and continues to do so.

There are some hurdles to innovation. For instance, success brings conservatism and then, there is the curse of high-volume manufacturing. It led to Andy Grove’s famous statement: “Only the paranoid survive”. Obviously, massive inertia and innovation do not blend. Rattner mentioned certain external hurdles, especially, anti-Innovation policies and standards that hamper innovation.

Moore’s Law drives innovation
Moore’s Law has been driving innovation at Intel. These have been in the form of high-K metal gate transistors at 45nm — the first new transistor architecture in 35 years! There’s more, in form of phase change memory (PCM) below 45nm, non-planar tri-gate transistor beyond 32nm, and carbon nanotube transistor

Some recent multi-disciplinary innovations include 45nm Core 2 Duo, Nehalem uArch, power management, quad core through package technology, Silverthorne/LPIA, USB/PCI Express, vPro, and WiMAX and 802.11n, respectively. Intel has made sustained Advances in silicon technology. In 2007, it developed 32nm SRAM with 1.9 billion transistors, with 32nm slated for 2009.

Sustained advances in micro-architecture include Intel Core — new microarchitecture 65nm (2006), Penryn compaction/derivative at 45nm (2007), Nehalem — new microarchitecture 45nm (2008), Westmere compaction/derivative 32nm (2009), and Sandy Bridge new microarchitecture 32nm (2010). “This shows our sustained microprocessor leadership,” added Rattner.

There are plans to further reinvigorate Intel architecture — by high throughput computing, IA programmability, ease of scaling for software, array of enhanced IA cores, and increasing teraflops of performance. Its 45nm Silverthorne is based on the Menlow platform and promises ‘Full Internet in Your Pocket.’

Intel has also made advances in integration and packaging, such as multi chip packages, Wifi + WiMAX, processor + chipsets + accelerators, 60 percent smaller CPU packages, and 100 percent lead-free technology*. By 2008, Intel is committed to having all 45nm CPUs halogen free.

Innovations in memory, communications
Intel has also made innovations in memory technology. Robson Technology, which has NAND Flash cache, has 1.5X faster application load times, has 1.5X resume from hibernate, gives 0.4W average power savings, and is used in the Santa Rosa platform.

The other innovation is solid-state drives. These are embedded in a range of devices, from handhelds to servers. Compared to HDDs, these give 1/10th the power, >10X performance, and are 1,000X more durable.

Innovations in communication technology include things like adaptive antenna and front-ends, digital CMOS radio, and reconfigurable baseband. Intel has also developed the world’s 1st TeraFLOPS supercomputer on a die. It features 80 cores, 1TFLOP at 62W, and 256 GB/s bisection.

Intel has also unleashed the era of tera. These are in the form of tera bits –- Si Photonics and tera bytes –- 3D stacked memory. The latter includes 256KB SRAM per core, 4X C4 bump density, and 3200 thru-silicon vias.

Similarly, Intel’s innovation in tera-scale software include RMS workloads, C++ for parallelism, Ct for nested data parallelism (race-free irregular parallel computation), and hardware assisted STM C transactional memory, which ensures concurrent access with no errors.

Intel has also done innovations for emerging regions. Rattner touched upon Research (at the Berkeley Lablet), which involves a long-distance WiFi solution: 6Mb/s at 100+ km. This has been tested at the Aravind Eye Hospital in Tamil Nadu. It has allowed doctor/patient videoconferences. Thirteen rural villages have been connected so far, going on to 50 villages. The impact has been tremendous — 2,500 exams per month, over 30,000 so far; cataracts, glaucoma, cornea problems have been diagnosed; and 3,000 people have had their vision restored so far.

Intel has also been a champion in innovating through collaboration. These have been in form of academic open-collaborative (pre-competitive research) — Carnegie Mellon, Berkeley, University of Washington; industrial partnerships (product differentiation) — an example being the ciscointelalliance.com, and consortium (ecosystem benefit) — via the ISA, Continua, Innovation Value Institute, Trusted Computing Group, etc.

Intel’s focus areas for 2008 include:
a) tera-scale computing — unleashing the next generation of applications.
b) Platform* on a chip (POC) — ‘Platform’ integration on chip with IA.
c) Trusted services — technologies for secure service opportunities.
d) Carry small, live large — context aware usage models and platforms.
e) Ultimate connectivity — connected ‘all-ways’ for future platforms.

Power awareness critical for chip designers

January 14, 2008 Comments off

The holy grail of electronics — low-power design, or having the requisite power awareness is extremely critical for chip designers working on both high-performance applications and portable applications. For one, it determines the battery lifetime of a device, besides determining the cooling and energy costs. It is said that several of today’s chip designs are limited in terms of power and still require maximum performance.

Touching on the global factors, S.N. Padmanabhan, Senior Vice President, Mindtree Consulting, said the Kyoto Protocol mandates energy conservation efforts.

Low-power design challenges
Asia, as we all know, has been emerging as a major energy consuming society. Shortage of electricity is becoming a major concern. There is a huge strain on nations to meet the rising needs/halt rise. There is also a rapid increase in all types of electronic goods in growing economies. As a result, increased efficiencies and reduced consumption should be beneficial as a whole!

In the Indian context, the country has around 125 million televisions sets, 5 million automatic washing machines, 10 million white goods, 200+ million other electronics, over 90 million cell phones and 50 million land lines, etc. A 1W reduction in white goods and TVs would lead to a saving of 140 Mi Watts of power! And, a 10 mW reduction in phones will save 1.4 Mi Watts!! Therefore, it makes even more sense to go low power!

Mindtree’s Padmanabhan said IC power budgets have come down drastically. It is <2W for four out of five chips designed. There has also been a simultaneous manipulation of multiple parameters (P=CV2f). Next, there are several leakage issues in 65nm and smaller geometries, which can no longer be ignored.

Add to all of these are factors that there is a lack of availability of comprehensive tools and techniques, as well as analog designs. In such a scenario, designers need to be very clear about their objectives — is it achieving lowering average power, lowering the maximum peak power or lowering energy.

Jayanta Kumar Lahiri, Director, ARM, pointed out challenges associated with batteries. Battery storage has been a limiting factor. Battery energy doubles in a decade and surely, does not follow the Moore’s law. Next, there have hardly been major changes in the basic battery technology. The energy density/size safe handling are limiting factors as well for batteries.

He added that the low-power challenge is four-fold in the VLSI domain. These are — leakiness; more integration means more W/cm^2; EDA tools not that good in low power domain and does not co-relate sometimes with the silicon, and variability of device parameters make things worse.

Toshiyuki Saito, Senior Manager, Design Engineering Division NEC Electronics Japan, said low power is necessary for customer’s success — in form of heat suppress for wired systems and improved battery life time for mobile systems. It also brings cost competitiveness for SoC suppliers in terms of packaging cost, and development cost and turnaround time. Finally, it would contribute to preserving the global environment.

Addressing low power challenges
What are semiconductor and EDA companies doing to address the low-power design challenges? Padmanabhan said several techniques were being employed at the circuit level. However, each one of those had limitations.

These include AVS — which provides maximum savings, reduces speed, but may need compensation; clock gating — which does not help to reduce leakage and needs additional gates; and adaptive clock scaling — which needs sophistication and is not very simple; and finally, the use of multi threshold cells for selective trade-off.

Emerging techniques include efficient RTL synthesis techniques, which is fast, but leaky, vs. slow and low power; power aware resource sharing, which is planning to be done at the architectural level and synthesis, but is not as widely used as other techniques; and power gating methodology — which makes use of sleep transistors, has coarse and fine grained methods, reduces dynamic and leakage power, and also exploits idle times of the circuit.

He added that power optimization should start at the architecture and design stages. Maximum optimization can be achieved at the system level. Also, the evolving power optimization tools and methodologies required collaborative approaches.

Power Forward Initiative
Pankaj Mayor, Group Director, Industry Alliances, Cadence Design Systems, said low power imperative is driving the semiconductor and EDA industries. He said, “design-based low power solution is the only answer!” Traditional design-based solutions are fragmented. Basic low power design techniques, such as area optimization, multi-Vt optimization and clock gating were automated in the 1990s.

There has since been an impact of advanced low-power techniques. These advanced techniques include multi-supply voltage (MSV), power shut-off (PSO), dynamic and adaptive voltage frequency scaling (DVFS and AVS), and substrate biasing. Cadence’s low-power solution uses advanced techniques.

According to Mayor, the Power Forward Initiative (PFI) has created an ecosystem as well. The Power Forward Initiative includes Cadence and 23 other companies across the design chain, as of the end of December 2007.

The year 2007 also saw a continued Power Forward industry momentum. In Q1-07, Common Power Format or CPF became the Si2 [Silicon Integration Initiative] standard. The Cadence Low Power Solution production released V 1.0 in this quarter as well. In H2-07, the industry has seen over 100 customers adopting CPF-based advanced low power solution as well as ~50 tapeouts.

CPF allows holistic automation and validation at every design step. Arijit Dutta, Manager, Design Methodology, Freescale Semiconductor exhibited the advantages of using the CPF in wireless, networking and automotive verticals at Freescale.

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