Exar Corp., established 1971, is headquartered in Fremont, USA, and has design centers in Silicon Valley and Hangzhou, China. Louis DiNardo, president and CEO, Exar, said that the company’s strategic model is to serve high-growth markets with innovative value-added solutions. He was speaking at the ongoing 13th Globalpress Electronics Summit in Santa Cruz, USA.
Exar offers solutions that includes high performance analog-mixed signal as well as data management solutions. Its current market focus is on networking and storage, industrial and embedded systems, and communications infrastructure. It is focusing on power management products, connectivity products and data management solutions.
Power management products include those for analog power management such as switching regulators, switching controllers, linear regulators, supervisory controllers, etc, For programmable power, Exar focuses on multiple output synchronous buck controllers.
Some of the products include POWER, the Exar Programmable PowerSuite 5.0. Recently, Calceda has been powering servers with the PowerXR technology.
For data compression and security, Exar is offering hardware acceleration and software solutions meant for compression and decompression, acceleration, encryption and decryption. There are high growth markets supporting social networking, industrial Internet and financial technology as well.
Exar’s Panther I is a first generation compression/security engine with the PCIe interface. The Panther II is a second generation compression and security engine with PCIe and FPGA interface.
IoT gathering pace as revolution: Guru Ganesan
By 2020, there will be over 8 billion people on our planet. This will also bring tremendous innovations and challenges. ARM has been connecting intelligence at every level, said Guru Ganesan, president and MD, ARM India.
He was delivering the guest keynote at the recently held CDNLive 2014 event in Bangalore, India.
Newer apps are helping connect with the world. As per Gartner, $27 billion worth apps were downloaded in 2013. By 2020, this is estimated to rise to $80 billion.
According to Ganesan, consumer trends are driving innovation in embedded apps, including rich user interface (UI). ARM is also at the heart of wearable technologies, for example, Smart Glasses from Google. Some examples from India include Lechal from Ducere Technologies, GOQ Pi remote fitness companion, Fin+ navigation and device control gesture based device from RHLVision, and Smarty Ring that brings instant smartphone alerts to your fingers from Chennai.
So, what are the key requirements for wearables? These are video/image, audio, display, software, OS, connectivity and battery life! In 2013, over 1 billion smartphones were shipped. Further, mobile data 12 times over between now and 2018.
In medical electronics, besides humans, it has extended to keeping the cattle healthy and have intelligent agriculture with OnFarm, by using sensors. IoT as a revolution is gathering pace. As per a survey conducted by ARM, 95 percent of the users expect to be using IoT over the next three years. Common standards are being developed for interoperability. Similarly, mobility and connectivity are also happening in automotives.
Now, let’s see the development challenges for high-end embedded. Embedded applications today integrate more functions. Consequently, design and verification challenges continue to grow. Further, lot of smart devices are now generating lot of data. The question is: how are we using that data?
Ganesan added that by 2020, there will be new challenges in transportation, healthcare, energy and education. Once devices start communicating with each other, we are likely to see the evolution of a smart infrastructure.
Engineers designing FPGA applications face many challenges. Using Plunify’s automation and analysis platform, engineers can run 100 times more builds, analyze a larger set of builds and quickly zoom in on better quality results. Using data analytics and the cloud, Plunify created new capabilities for FPGA design, with InTime being an example.
Kirvy Teo said: What happens when you need to close timing in FPGA design and still can’t get it to work? Here is a new way to solve that problem – machine learning and analytics. InTime is an expert software that helps FPGA design engineers meet timing and area goals by recommending “strategies”. Strategies are combination of settings found in the existing FPGA software. With more than 70 settings available in the FPGA software, no sane FPGA design engineer have the time or capacity to understand how these affect the design outcomes.
One of the common methods now is to try random bruteforce using seeds. This is a one-way street. If you get to your desired result, great! If not, you would have wasted a bunch of time running builds with you none the wiser. Another aspect of running seeds is that the variance of the results is usually not very big, meaning you can’t run seeds on a design with bad timing scores.
However, using InTime, all builds become part of the data that we used to recommend strategies that can give you better results, using machine learning and predictive analytics. This means you will definitely get a better answer at the end of the day, and we have seen 40 percent performance improvements on designs!
How has Plunify been doing this year so far? According to Teo, Plunify did a controlled release to selected customers in first quarter of 2014, who are mainly based in China. It is easier to guess who as we nicknamed them “BCC” – Big Chinese Corporations.
Unsurprisingly, they have different methodologies to solving timing problems and design guidelines, many of which were done to pre-empt timing problems at the later stage of the design. InTime was a great way to help them to achieve their performance targets without disrupting their tool flows.
Plunify is announcing the launch of InTime during DAC and will be looking to partner with sale organizations in US.
What’s the future path likely to be? Teo added: “Machine learning and predictive analytics are one of the hottest topics and we have yet seen it being used much in chip design. We see a lot of potential in this sector. Beyond what InTime is doing now, there are still many chip design problems that can be solved with similar techniques.
“First, there is a need to determine the type of problems that can be solved with these techniques. Second, we are re-looking at existing design problems and wondering, if I can throw 100 or 1000 machines to this problem, can I get a better result? Third, how to get that better result without even running it!
“As you know, we do offer a FPGA cloud platform on Amazon. One of the most surprising observations is that people do not know how to use all those cheap power in the cloud! FPGA design is still confined to a single machine for daily work, like email. Even if I give you 100 machines, you don’t know how to check your emails faster! We see the same thing, the only method they know is to run seeds. InTime is what they need to make use of all these resources intelligently.
Why would FPGA providers take up the solution?
The InTime software works as a desktop software which can be installed in internal data centers or desktops. It is on longer just a cloud play. It works with the current in-house FPGA software that the customer already own. We are helping FPGA providers like Xilinx or Altera, by helping their customers with the designs. They will feel: How about “Getting better results without touching your RTL code!”
Optic2Connect will be present at this year’s DAC. I caught up with Sean Seah, project manager, to find out more.
First, what’s the company’s X factor and why? (What is it that makes your offering special and noteworthy – how are you different from competitors)?
Optic2Connect develops software solutions for the photonics industry. The demand to manage high volumes of data in networks, especially with the current smart-phone and cloud computing trend, has increased tremendously. As design gets more complex, simulation tools need to scale with regard to fidelity and accuracy.
Currently, photonic designers, scientists, and fabrication engineers adopt an approximated approach from the electrical data to build an equivalent optical model, hence losing on device physics details. At the same time the process is long as the model needs to be described block-by-block with denser blocks representing a more detailed model. Our competitors are well established in their respective domains, electrical or optical, but they are strong in their own respective fields. However, intimate knowledge in both are essential to fully understand this newer generation of photonic devices. Failure to understand fully results in false results from the manufacturing.
With patented know-how, Optic2Connect provides software solutions that SOLVES this pertinent challenge. It maps accurately simulations from one domain to another, e.g. electrical to optical. This technology has been developed by a team of researchers at A*Star – Singapore Public Research Institute. The technology overcomes error-prone and detailed oriented simulation setups. We demonstrated the ability to map without losing any fidelity in the simulation files.
Optic2Connect’s IP differs from its competitors because it simulates directly from the beginning device processing, to electrical device performance until the final high-speed optical eye diagram. This is in stark contrast to the usual method of representing their operation using simplified transfer functions.
Furthermore, the Optic2Connect design flow uses the same reliable tools and processes from the semiconductor industry that are fully compatible with the Complementary Metal Oxide Semiconductor (CMOS) fabrication process of silicon microelectronics. This design flow uses standard tools libraries, device models especially for active components such as modulators, and simulation of these components incorporating the models.
How have you been doing this year so far? Seah said: “It has been excellent! We are racing to complete our product prototypes and we secured a contract from an MNC and another from universities.”
What’s the future path likely to be? Seah added: “We intend to further validate our prototype with our partners from industry and academia, and integrating advanced modulation formats into our solutions. We want to offer a fully integrated solution for photonic devices to our customers. Our goal is to offer a one-stop solution for leading integrated-circuit (IC) manufacturers!”
Why this name? You sounded like a telecom company!
Seah said: “We strongly believe the future of communications is via optics which has the ability to circumvent the data bottleneck issues. Optic2Connect is meant to offer connect using optical communications. Our goal is a one-stop solution for optical connections. ”
How will the solution significantly shorten product time-to-market and reduce development costs of photonics devices?
For complex photonics devices, minute changes to design parameters are significant and could affect loss performance, and operating voltage requirements. One common approach in the industry today is to physically build the variations into multiple device / runs and test them out. Each run cost is the range of hundreds of thousands and consume precious time. Especially, if the first batch of devices do not meet required parameters and additional batches are required. This cost both money and time, which in turn is more money.
Hence, Optic2Connect provides an elegant solution with our accurate modelling and simulation solutions, this accelerates manufacturing prototypes and at much lower production costs. Our software solutions provide a 10x improvement in time reduction and time to market. Further, our cloud solution overcomes traditional problems of insufficient servers / licenses, especially during periods of peak demand.
Renesas Electronics recently opened its India subsidiary in Bangalore. Elaborating, Sunil Dhar, managing director of Renesas Electronics India said: “We are glad to announce the opening of Renesas Electronics India Pvt Ltd, a wholly-owned subsidiary of Renesas Electronics Singapore Pte Ltd., located in Bangalore.
“Since 2010, Renesas has been providing technical product support to its customers here via branch offices in Bangalore, Delhi and Mumbai. As part of its expansion plan, Renesas will turn our said branches into a full subsidiary.
“The branch office setup served us well when the organization was small and its role was limited. In order to expand further in terms of opening more offices in India for close customer support, and to be able to provide wider services to customers in India like reference software, hardware, reference solutions which would be developed in India, it would require us to have a permanent establishment here.
“Through this new company, we aim to expand business by providing the best solution offerings and technical support as well as a regional systems solution development expertise to the Indian market.”
How does the India R&D team play a role in global innovation and where do you see Renesas Electronics in India five years from now?
He said that over 50 percent of the Renesas India team is application development or field engineers armed with knowledge of embedded hardware and software development and support.
In order to expand the footprint in Indian markets, Renesas plans to build up a strong application engineering team. India Application engineering team will engage with the Renesas headquarters, regional offices to develop new products and solutions dedicated for emerging countries, including India.
The application engineering team and the future solution centre aim to survey the market for solution needs, prepare India designed solutions fitting the price points and specifications points as required in the Indian market. Along with the customers, the team also intends to collaborate with the design houses to create innovative solutions addressing upcoming needs of the market. Our goal is to become the most trusted semiconductor solution provider in India.
What are the India-centric solutions that would be developed from the India Application Engineering team?
Dhar added that the needs of emerging markets are usually different in both specifications as well as price points. By providing dedicated local support via the new company, and with a focus on industrial and automotive applications for two- and four-wheelers, Renesas aims to increase its MCU share in India and expand its solution offerings with rich lineup of kit solutions (MCU + SoC + power devices) and platform reference boards (boards with complete ecosystem including devices and software) to provide customers a shorter time-to-market.
The team will initially focus on automotive and particularly, two-wheeler solutions. The intention is to expand the scope of the application engineering team’s activity to industrial and consumer appliances in near term.
What is the overall India employee strength? How are the investment plans looking up?
Dhar said: “In order to expand our footprint in Indian markets, we will double our headcount in near term. Currently, we are just under 30 staff and over 50 percent of us are application development or field engineers armed with the knowledge of embedded hardware and software development and support. Upon setting up the organization in Sales and Marketing roles in the initial days, we also have plans to announce the setting up of a Solutions Centre in India to develop reference application solutions to enable our customers to use our devices.
“We are intending to invest in lab, infrastructure setup and expansion of activities in the next three to five years. Additionally, we are also considering investing towards 3rd party and IDH for enlarged business engagement.”
Trends driving automotive market in India
Regarding trends driving the automotive market in India, Dhar said that Renesas focusses on three business segments – automotive, industrial and home, OA and ICT. Renesas holds more than 40 percent global market share for automotive MCU business. Our target applications for automotive segment are automotive control and automotive infotainment and network.
Renesas has dedication applications solutions for integrated cockpit through system on chip, R-car ecosystem collaboration solution for e-mobility and automotive analog and power devices for driving, steering and braking.
As semiconductor technologies evolved, it has enabled automakers to integrate multiple applications on a single chip significantly reducing the board area; thus optimizing performance and adding new features for comfort, safety and infotainment. Power technologies have brought energy efficiency, limiting power consumption in vehicles. Advancements in process technologies will continue to drive the auto industry in the coming years.
Renesas, for instance, developed the industry’s first 28nm flash memory IP for MCUs and the first semiconductor supplier to move from 40nm to 28nm process technology.
“Trends driving auto industry in India and globally are more of less the same. However, for India market, we see a specific demand for two-wheeler solutions and that is our target in coming years,” he concluded.
Lastly, I must take the opportunity to thank Ms Shweta Dhadiwal-Baid and Ms Sharmita Mandal for making this happen!😉
This is the third installment on verification, now, taken up by Synopsys. Regarding the biggest verification mistakes today, Arindam Ghosh, director – Global Technical Services, Synopsys India, attributed these as:
* Spending no time on verification planning (not documenting what needs to be verified) and focusing more on running simulations or on execution.
* No or very low investment in building better verification environments (based on best/new methodologies and best practices); instead maintaining older verification environments.
* Compromising on verification completeness because of tape out pressures and time-to-market considerations.
Would you agree that many companies STILL do not know how to verify a chip?
He said that it could be true for smaller companies or start-ups, but most of the major semiconductor design engineers know about the better approaches/methodologies to verify their chips. However, they may not be investing in implementing the new methodologies for multiple reasons and may instead continue to follow the traditional flows.
One way to address these mistakes would be to set up strong methodology teams to create a better verification infrastructure for future chips. However, few companies are doing this.
Are companies realizing this and building an infrastructure that gets you business advantage? He added that some companies do realize this and are investing in building a better infrastructure (in terms of better methodology and flows) for verification.
When should good verification start?
When should good verification start — after design; as you are designing and architecting your design environment? Ghosh said that good verification starts as soon as we start designing and architecting the design. Verification leads should start discussing the verification environment components with the lead architect and also start writing the verification plan.
Are folks mistaking by looking at tools and not at the verification process itself? According to him, tools play a major role in the effectiveness of any verification process, but we still see a lot of scope in methodology improvements beyond the tools.
What all needs to get into verification planning as the ‘right’ verification path is fraught with complexities? Ghosh said that there is no single, full-proof recipe for a ‘right’ verification path. It depends on multiple factors, including whether the design is a new product or derivative, the design application etc. But yes, it is very important to do comprehensive verification planning before starting the verification process.
Synopsys is said to be building a comprehensive, unified and integrated verification environment is required for today’s revolutionary SoCs and would offer a fundamental shift forward in productivity, performance, capacity and functionality. Synopsys’ Verification Compiler provides the software capabilities, technology, methodologies and VIP required for the functional verification of advanced SoC designs in one solution.
Verification Compiler includes:
* Better capacity and compile and runtime performance.
* Next-generation static and formal technology delivering performance improvement and the capacity to analyze a complete SoC (Property checking, LP, CDC, connectivity).
* Comprehensive low power verification solution.
* Verification planning and management.
* Next-generation verification IP and a deep integration between VIP and the simulation engine, which in turn can greatly improve productivity. The constraint engine is tuned for optimal performance with its VIP library. It has integrated debug solutions for VIP so one can do protocol-level analysis and transaction-based analysis with the rest of the testbench.
* Support for industry standard verification methodologies.
* X-propagation simulation with both RTL and low power simulations.
* Common debug platform with better debug technology having new capabilities, tight integrations with simulation, emulation, testbench, transaction debug, power-aware debug , hw/sw debug, formal, VIP and coverage.
Top five recommendations for verification
What would be Synopsys’ top five recommendations for verification?
* Spend a meaningful amount of time and effort on verification planning before execution.
* Continuously invest in building a better verification infrastructure and methodologies across the company for better productivity.
* Collaborate with EDA companies to develop, evaluate and deploy new technologies and flows, which can bring more productivity to verification processes.
* Nurture fresh talent through regular on and off-the-job trainings (on flows, methodologies, tools, technology).
* Conduct regular reviews of the completed verification projects with the goal of trying to improve the verification process after every tapeout through methodology enhancements.
Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. 😉 I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification mistakes.
Top verification mistakes
Kalia said that the biggest verification mistakes made today are:
* Verification engineers do not define a structured notion of verification completeness.
* Verification planning is not done up front and is carried out as verification is going along.
* A well-defined reusable verification methodology is not applied.
* Legacy tools continue to be used for verification; new tools and technologies are not adopted.
In that case, why are some companies STILL not knowing how to verify a chip?
He added: “I would not describe the situation as companies not knowing how to verify a chip. Instead, I think a more accurate description of the problem is that the verification complexity has increased so much that companies do not know how to meet their verification goals.
“For example, the number of cycles needed to verify a current generation processor – as calculated by traditional methods of doing verification – is too prohibitive to be done in any reasonable timeframe using legacy verification methodologies. Hence, new methodologies and tools are needed. Designs today need to be verified together with software. This also requires new tools and methodologies. Companies are not moving fast enough to define, adopt and use these new tools and methodologies thereby leading to challenges in verifying a chip.”
How are companies trying to address the challenges?
Companies are trying to address the challenges in various ways:
* Companies at the cutting edge of designs and verification are indeed trying to adopt structured verification methodologies to address these challenges.
* Smaller companies are trying to address these challenges by outsourcing their verification to experts and by hiring more verification experts.
* Verification acceleration and prototyping solutions are being adopted to get faster verification and which will allow companies to do more verification in the same amount of time.
* Verification environment re-use helps to cut down the time required to develop verification environments.
* Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.
Cadence has the widest portfolio of tools to help companies meet verification challenges, including:
Incisive Enterprise Manager, which provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility;
The recently launched vManager solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity;
Incisive Enterprise Verifier, which delivers dual power from tightly integrated formal analysis and simulation engines; and
Incisive Enterprise Simulator, which provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization.
Are companies building an infrastructure that gets you business advantage? Yes, companies are realizing the problems. It is these companies that are the winners in managing today’s design and verification challenges, he said.
When should good verification start?
Kalia noted: “Good verification should start right at the time of the high level architecture of the design. A verification strategy should be defined at that time, and an overall verification plan should be written at that time. This is where a comprehensive solution like Incisive vManager can help companies manage their verification challenges by ensuring that SoC developers have a consistent methodology for design quality enhancements.”
Are folks mistaking by looking at tools and not at the verification process itself?
He addded that right tools and methodology are needed to resolve today’s verification challenges. Users need to work on defining verification methodologies and at the same time look at the tools that are needed to achieve verification goals.
Finally, there’s verification planning! What should be the ‘right’ verification path?
Verification planning needs to include:
* A formal definition of verification goals;
* A formal definition of coverage goals at all levels – starting with code coverage all the way to functional coverage;
* Required resources – human and compute;
* Verification timelines;
* All the verification tools to be used for verification; and
* Minimum and maximum signoff criteria.
It seems to be the season of verification. The Universal Verification Methodology (UVM 1.2) is being discussed across conferences. Dennis Brophy, director of Strategic Business Development, Mentor Graphics, says that UVM 1.2 release is imminent, and UVM remains a topic of great interest.
Biggest verification mistakes
Before I add Dennis Brophy’s take on UVM 1.2, I discussed with Dr. Wally Rhines, chairman and CEO, Mentor Graphics Corp. the intricacies regarding verification. First, I asked him regarding the biggest verification mistakes today.
Dr. Rhines said: “The biggest verification mistake made today is poor or incomplete verification planning. This generally results in underestimating the scope of the required verification effort. Furthermore, without proper verification planning, some teams fail to identify which verification technologies and tools are appropriate for their specific design problem.”
Would you agree that many companies STILL do not know how to verify a chip?
Dr. Rhines added: “I would agree that many companies could improve their verification process. But let’s first look at the data. Today, we are seeing that about 1/3 of the industry is able to achieve first silicon success. But what is interesting is that silicon success within our industry has remained constant over the past ten years (that is, the percentage hasn’t become any worse).
“It appears that, while design complexity has increased substantially during this period, the industry is at least keeping up with this added complexity through the adoption of advanced functional verification techniques.
“Many excellent companies view verification strategically (and as an advantage over their competition). These companies have invested in maturing both their verification processes and teams and are quite productive and effective. On the other hand, some companies are struggling to figure out the entire SoC space and its growing complexity and verification challenges.”
How are companies trying to address those?
According to him, the recent Wilson Research Group Functional Verification Study revealed that the industry is maturing its verification processes through the adoption of various advanced functional verification techniques (such as assertion-based verification, constrained-random simulation, coverage-driven techniques, and formal verification). Complexity is generally forcing these companies to take a hard look at their existing processes and improve them.
Getting business advantage
Are companies realizing this and building an infrastructure that gets you business advantage?
He added that in general, there are many excellent companies out there that view verification strategically and as an advantage over their competition, and they have invested in maturing both their verification processes and teams. On the other hand, some other companies are struggling to figure out the entire SoC space and its growing complexity and verification challenges.
When should good verification start?
When should good verification start — after design; as you are designing and architecting your design environment?
Dr. Rhines noted: “Just like the design team is often involved in discussion during the architecture and micro-architecture planning phase, the verification team should be an integral part of this process. The verification team can help identify architectural aspects of the design that are going to be difficult to verify, which ultimately can impact architectural decisions.”
Are folks mistaken by looking at tools and not at the verification process itself? What can be done to reverse this?
He said: “Tools are important! However, to get the most out of the tools and ensure that the verification solution is an efficient and repeatable process is important. At Mentor Graphics, we recognize the importance of both. That is why we created the Verification Academy, which focuses on developing skills and maturing an organization’s functional verification processes.”
What all needs to get into verification planning as the ‘right’ verification path is fraught with complexities?
Dr. Rhines said: “During verification planning, too many organizations focus first on the “how” aspect of verification versus the “what.” How a team plans to verify its designs is certainly important, but first you must identify exactly what needs to be verified. Otherwise, something is likely to slip through.
“In addition, once you have clearly identified what needs to be verified, it’s an easy task to map the functional verification solutions that will be required to productively accomplish your verification goals. This also identifies what skill sets will need to be developed or acquired to effectively take advantage of the verification solutions that you have identified as necessary for your specific problem.”
How is Mentor addressing this situation?
Mentor Graphics’ Verification Academy was created to help organizations mature their functional verification processes—and verification planning is one of the many excellent courses we offer.
In addition, Mentor Graphics’ Consulting provides customized solutions to technical challenges on real projects with real schedules. By helping customers successfully integrate advanced functional verification technologies and methodologies into their work flows, we help ensure they meet their design and business objectives.
Five recommendations for verification
Finally, I asked him, what would be your top five recommendations for verification?
Here are the five recommendations for verification from Dr. Rhines:
* Ensure your organization has implemented an effective verification planning process.
* Understand which verification solutions and technologies are appropriate (and not appropriate) for various classes of designs.
* Develop or acquire the appropriate skills within your organization to take advantage of the verification solutions that are required for your class of design.
* For the SoC class of designs, don’t underestimate the effort required to verify the hardware/software interactions, and ensure you have the appropriate resources to do so.
* For any verification processes you have adopted, make sure you have appropriate metrics in place to help you identify the effectiveness of your process—and identify opportunities for process improvements in terms of efficiency and productivity.
I recently met Sam Fuller, CTO, Analog Devices, and had an interesting conversation. First, I asked him about the state of the global semicon industry in 2013.
Industry in 2013
He said: “Due to the uncertainties in the global economy in the last couple of years, the state of the global semiconductor industry has been quite modest growth. Because of the modest growth, there has been a buildup in demand. As the global economies begin to be more robust going forward, we expect to see more growth.”
Industry in 2014?
How does Analog Devices see the industry going forward in 2014? What are the five key trends?
He added: “I would talk about the trends more from an eco-system and applications perspective. Increased capability on a single chip: Given all the advances to Moore’s law, the capability of a chip has increased considerably in all dimensions and not just performance, be it the horsepower we see in today’s smartphones or the miniaturization and power consumption of wearable gadgets that were on show this year at CES.
“In Analog Devices’ case, as we are focused on high performance signal processing, we can put more of the entire signal chain on a single die. For our customers, the challenge is to provide their customers a more capable product which means a more complex product, but with a simpler interface.
“A classic example is our AD9361 chip, which is a single chip wideband radio transceiver for Software Defined Radio (SDR). It is a very capable ASSP (Application Specific Standard Products) as well as RF front end with a wide operating frequency of 70 MHz to 6 GHz.
“This chip, coupled with an all-purpose FPGA, can build a very flexible SDR operating across different radio protocols, wide frequency range and bandwidth requirements all controlled via software configuration. It finds a number of applications in wireless communication infrastructure, small cell Base stations as well as a whole range of custom radios in the industrial and aerospace businesses.”
Now, let’s see the trends for 2014!
More collaboration with customers: There is a greater emphasis on understanding customers’ end applications to provide a complete signal chain, all in a System on a Chip (SoC) or a System in a package (SiP). The relationship with our customers is changing as we move more towards ASSPs focused with few lead customers for target markets and target applications. While this has already been ongoing in the consumer industry with PCs and laptops, customers in other vertical markets like healthcare, automotive and industrial are and will collaborate more with semiconductor companies like Analog Devices to innovate at a solutions level.
More complete products: We have evolved from delivering just the silicon at a component level to delivering more complete products with more advanced packaging for various 3D chips or multi-die within a package. Our solutions now have typically much more software that makes it easier to configure or program the chips. It is a solution that is a combination of more advanced silicon, advanced packaging and more appropriate software.
With providing the complete solution, the products are more application specific and hence, the need for more collaboration with customers. For example, there may be one focused on Software Defined Radio, one for motor control, and one for vital signs monitoring for consumer health that we have launched recently.
We need it to be generic enough that multiple customers can use it, but it needs to be as tailored as possible to the customers’ needs for specific market segments. While because of the volume and standardization, availability of complete reference designs in the consumer world has been the norm, other market segments are demanding more complete products not-withstanding the huge variation in protocols and applications.
Truly global industry: The semiconductor and electronics industry has become truly global, so multiple design sites around the globe collaborate to create products. For example for Analog Devices, one of our premier design sites is our Bangalore product design center where we quite literally developed our most complex and capable chips. At the same time our customers are also global.
We see large multinational companies like GE, Honeywell, Cisco, Juniper, ABB, Schneider and many of our top strategic customers globally doing substantial system design work in Bangalore along with a multitude of India design houses. Our fastest growing region is in Asia, but we have substantial engagement with customers in North America and Europe. And our competition is also global, which means that the industry is ever moving faster as the competition is global.
Smarter design tools: The final trend worth talking about is the need for smarter design tools. As our products and our customers’ products become more complex and capable, there have to be rapidly developing design tools, for us to design them.
This cannot be done by brute force but by designing smarter and better tools. There is a lot of innovation that goes on in developing better tool suites. There is also ever more capable software that caters to a market moving from 100s of transistors to literally billions of transistors for an application.