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Mentor on EDA trends and solar/PV

September 24, 2008 Comments off

This is a continuation of my recent discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

There have been whispers that the EDA industry has been presently lagging behind semiconductors and is in the catch-up mode. “That’s a matter of perspective. There are definitely unsolved challenges at 32nm and 22nm, but the reality is that we are still in the technology development stage,” he says.

For EDA tools that address implementation and manufacturing issues (i.e., Mentor design-to-silicon products), there are dependencies that cannot be fully resolved until the process technology has stabilized. Mentor Graphics is laying the groundwork for those challenges and working in concert with the process technology leaders to ensure that our products address all issues and are production-worthy before the process technology goes mainstream.

On the other hand, although Mentor’s products are fully-qualified for 45nm, there have only been a handful of tapeouts at that node, so for the majority of customers, we are ahead of the curve.

On ESL and DFM as growth drivers
ESL and DFM are said to be the new growth drivers. Sawicki adds: “As Wally Rhines has said in his public presentations, system level design and IC implementation are the stages of development where there are the most challenges, and therefore the most opportunities. To continue the traditional grow spiral that the electronic industry has enjoyed as a result of device scaling, we need more sophisticated EDA solutions to deal with both of these challenges.”

ESL is responding to the growth of design complexity and the need for earlier and more thorough design verification, including low power characteristics, and software integration.

The Design-to-Silicon division is addressing the issues of IC implementation which result not only from the increase in design complexity and devices sizes, but also from increasing sensitivity of the manufacturing process to physical design decisions, a phenomenon often referred to as “manufacturing variability.”

Although the term “Design-For-Manufacturing” reflects the need to consider manufacturability in design and to optimize for both functional and parametric yield, it is important to emphasize that DFM is not simply an additional tool or discrete step in the design process, but rather an integration of manufacturing process information throughout the IC implementation flow.

With single threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out. It would be interesting to see how is Mentor handling this.

According to Sawicki, Mentor has incorporated sophisticated multi-threading and multi-processing technologies into all of its performance-sensitive applications, from place-and-route, through physical verification, resolution enhancement and testing.

He says, “Our tools have a track record of impressive and consistent and performance and scalability improvements, which is why we continue to lead the industry in performance.”

In addition to merely adding multi-threading and support for multi-core processors, Calibre products have a robust workflow management environment that automatically distributes the processing workload in the most efficient manner across any number of available clustered computing nodes.

Mentor’s Olympus-SoC place-and-route is inherently scalable due to its advanced architecture which includes an extremely efficient graph representation for timing information, and a very concise memory footprint. In addition, all the engines within Olympus-SoC can take advantage of multi-threaded and multi-core processors for high performance. These features enable Olympus-SoC to handle 100M+ gates designs in flat mode without excessive turnaround time.

Mentor’s ATPG tools are also designed to operate in multiprocessing mode over the multiple computing platforms to reduce test pattern generation time. In addition, Mentor test pattern compression technology reduces test pattern volume and test time, making it feasible to fully test 100M gate devices and maintain product quality without an explosion in test cost.

With EDA is starting to move up to the system level, will this make EDA less dependent on the semiconductor world?

Sawicki agrees that there are challenges at both the front end and back end of the electronic products design and manufacturing life cycle. Both of these opportunities are growing. In addition, developments like multi-level (3D) die packaging, through-silicon via (TSV) structures and other non-traditional techniques for device scaling are pushing system and silicon design issues closer together.

Reaching the 22nm node will require highly compute intensive EDA techniques for physical design to compensate for limitations in the manufacturing process. Beyond that, we could see a major shift to new materials and manufacturing techniques that would open new green fields for EDA in the IC implementation flow.

EDA going forward
How does Mentor see the EDA industry evolving, going forward?

Sawicki adds: “There are three key trends to watch. Firstly, for design to remain affordable at the leading edge, we need to enable radical increases in productivity. Electronic System Level (ESL) design is the key here, allowing designers to move to a new level of abstraction for both design and verification.

“Secondly, the challenges of manufacturing a well-yielding and reliable device as we move to 22nm will require a far more sophisticated physical implementation environment—one that accounts for physical effects in the design loop, and accounts for manufacturing variability in it’s optimization routines.

“Finally, the manufacturing challenges also open significant opportunity for EDA in the manufacturing space. A great example of this is the September 17, 2008 announcement we did with IBM on a joint development program to enable manufacturing at the 22nm node.”

Finally, given the roles already defined by Magma and Synopsys in solar, is there an opportunity for EDA in solar/PV?

According to Sawicki, as the photovoltaic devices have very simple and regular structures, most of the opportunity for EDA is not in logic design tools, but in material science, transistor-level device modeling, and manufacturing efficiencies with a focus on conversion efficiency and manufacturing cost reduction.

EDA’s role in solar will be in the newer areas related to Design-for-Manufacturing and other manufacturing optimizations, he concludes.

Our last discussion on DFM will follow in a later blog post!

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Semicon special: Global and Indian scenarios, design trends

June 15, 2008 Comments off

I’ve been blogging on semicon for some time now, and it is also going to be a year since the CIOL Semicon site was launched.

This special edition looks at the global semiconductor scenario — how is the industry dealing with the ‘deep trauma’ it finds itself in, along with certain forecasts. Will the recession bring the industry down, or is there light at the end of the tunnel? We also look at some predictions made in the past and evaluate where the semiconductor industry stands today.

In the Indian context, the special analyzes India’s growing might in the global semiconductor market, the emergence of India as an embedded superstar, the growing strength of the Indian design services segment, and a quick look at how planners need to take the semicon policy forward.

The special also addresses some leading design trends, such as the use of graphical system design for embedded control systems, trends in video compression, and why designers and developers need to go parallel. It also touches on some recent developments in 22nm.

All articles can be found on the CIOL Semicon site. Some of the posts are available on my blog as well. Enjoy!

Global Semiconductor Market Scenario

1. Top 10 global semicon predictions: where are we today
While the chip industry is equipped to take on the challenges ahead, do watch out for weaker DRAM and NAND markets.

2. Semicon likely to grow 12pc in 2008
If there will be an economic recession, the chip industry (but not all firms) is in the best shape possible to weather the ensuing storm.

3. Semi trends 2008: Fab spend lower, ASPs stabilizing
The call on global fab spend was for a 10 percent reduction, and this is now getting to be closer to 20 percent.

4. Global semicon to grow 4.9pc
These forecasts are based on April’s WSTS sales numbers, as per the Cowan LRA (Linear Regression Analysis) model.

Indian Semiconductor Market Scenario

1. India’s growing might in global semicon
India is fast becoming the world’s destination, and increasingly the source too, for semiconductors.

2. Indian design services to touch $10.96bn by 2010
Total design services market in India is said to have grown at 21 percent year on year.

3. Indian semicon industry creating its niche
The Indian semiconductor industry has established itself as a leading provider for design services outsourcing.

4. Indian semicon needs concrete planning
India should produce a good plan to take semiconductors forward and be realistic about what can be done.

5. India the emerging embedded superstar
We are witnessing a strong trend from companies slowly moving from ‘Service Only’ model to ‘Service + Product/IP’ model.

6. Emerging trends in embedded market
High-performance, low-power embedded systems are moving to platforms based on multicore and mobile processors with low thermals.

7. IBM-Telelogic to extend embedded offerings
Acquisition of Telelogic fortifies Rational development at India Software Lab, opens door for company to gain foothold in embedded.

8. EDA healthy and growing in India
Consumption of EDA technologies is growing in regions outside of the US and Europe.

Semiconductor Design Trends

1. Graphical system design for embedded control systems
Graphical system design (GSD) is a revolutionary approach to embedded design that blends intuitive graphical programming and flexible commercial off-the-shelf (COTS) hardware.

2. Video compression: trends in encoding/decoding chips
High-quality video transmission is creating challenges for designers, and this article seeks to address these challenges.

3. Be parallel, or perish!
Parallelism offers new doors, and creativity is required to open these new doors, says Intel.

4. Fascinating developments in 22nm!
These augur well for the global semiconductor industry, even though the field could get much narrower.

Semicon to grow 12pc in 2008: Future Horizons

May 14, 2008 Comments off

If there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm!

According to Malcom Penn, CEO, Future Horizons, we are dealing with a semiconductor industry in ‘deep trauma.’ He was delivering the company’s forecast at the recently held International Electronics Forum (IEF) 2008 in Dubai, predicting a 12 percent growth this year despite signs of a wobbling US economy.

Is there a need to get back to the industry basics? “Semiconductors are a peculiar business; the only sane strategy is to bet the company regularly,” once remarked Dr Gordon Moore.

Penn noted that the current industry status is somewhat confused and uncertain. Short-term issues are dominating the agenda.

Longer-term structural trends are unclear. The traditional IDMs are currently going through a mid-life ‘new business model’ identity crisis, and the start-ups are struggling to even reach critical mass! And all of this has been happening amidst intense economic uncertainty

“Now is the time for strong nerves and determination,” Penn said. According to him, the underlying industry fundamentals are sound and there is no end in sight to the ‘make-lunch-or-be-lunch’ ethos.

The emerging economies like India and China have so far been less affected by the financial market’s turbulence. In fact, the emerging and developing economies were shifting the global growth dynamics.

Chip industry in best possible shape
A forecast health warning is: IF the global economy collapses, it will take the chip market with it. However, Future Horizons feels that if there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm.

The ASPs are an enigma wrapped up in riddle. The course of ASPs (like love) never runs smooth. Wobbles happen! ASPs are also the perennial (and least understood) industry wild card. ASPs are generally driven by new IC designs, and that takes time (sometimes three to four years). Post-2001, value recovery lost one generation (130nm impact). The ASP recovery ‘wobbled’ in 2007 (memory and MPU price wars). Barring a recession, Future Horizons forecasts that ASPs will recover in 2008 (it has already started).

12 percent growth likely
Future Horizons’ 2008 forecast summary and assumptions (as of May 2008) are — ‘12 percent’ growth — ’10 percent’ units / ‘2 percent’ ASP. There may be no global economic recession, although US/UK/Eurozone might wobble — which they are! No significant inventory correction will probably take place, but there are always Q4>Q1 adjustments, and there’s nothing special about that either.

There could be lower fab capacity expansion due to 2007/2008 capex slowdown, which is inevitable and irreversible. There is also a possibility of a more stable memory price erosion — which means, back to the learning vs. bleeding curve, and prices have since hardened. If the global economy holds, the 2H-08 growth will likely be strong. This, if the capacity, ASP and units are all pulling together, which is said to be happening.

Therefore, Penn feels it is too early to call for a (major) downward revision. Q1 08 was a lot stronger than conventional wisdom feared.

“That’s the rational analysis, but semiconductors aren’t rational. It could just as easily be another single digit growth year,” Penn added.

Danger signs to watch out for
So, what are the danger signs one should watch out for? These would be capacity — it is hard to see how this can spoil 2008, provided unit growth holds up, but there is a need to watch capex. Another factor is demand — the current IC unit demand is sustainable provided the economy holds up, so there is a need to watch the inventory.

Next comes the economy! The current outlook continues to be uncertain with risks all on the downside. ASPs are the key to recovery, but always the first line of defence. ASPs could still derail 2008, but the trends are encouraging.

What’s driving the market?
In semiconductor 7.0 — or the 7th decade of the transistor revolution, the same things, as always, are driving the market. These are: technology, legislation — energy saving/conservation and structural — the relentless analog to digital conversion. All of these are combining to do what the chip industry does best — enabling something that was previously impossible. Penn contends, “This industry has nowhere near run out of steam!”

New applications continue to drive the market, with automotive, industrial and medical, mobile phones, and PCs and servers, dominating. The PC market is dominating, but going nowhere fast. Mobile phones have become more interesting, but have conflicting priorities. The challenges are: how to protect the existing cost structure and subscriber base and how to add useful and affordable value-add services! Evidently, “chipset suppliers love the high end, market loves the low end.”

There is definitely an increasing automotive semiconductor content. A solid annual growth has been prediced (CAGR 2006-11) for vehicles — 5.5 percent, systems — 11.5 percent, and semiconductors — 13.3 percent. Some other new areas are motor control and energy, as well as lighting and photovoltaic, besides medical electronics. Robotics is yet another interesting area.

Key industry issues
It is clear that more chips per wafer equals less cost per chip and more transistors per die equals more functionality. Several billion transistors gives phenomenal design flexibility as well. Considering total ICs and MOS ICs, in the MOS capacity build out by technology node, there has been no change in volume ramp profile despite the hype.

As for the evolution of the technology node, definitely, 45nm is a revolutionary step from 65nm. In all likelihood, 32nm will be a natural evolutionary. However, Penn cautioned that 22nm would be another ‘difficult’ transition!

There is no doubt that 65nm will be tomorrow’s leading-edge workhorse, having the same basic Si gate/SiO2/MOSFET structure. Nevertheless, 45nm will herald a totally different structure — metal gate/high-k/thin FET/deep trench design, etc. Also, 45nm will herald a new way of system design.

Is fabless right?
Is Fablite a valid option? While there is nothing wrong with being fabless, people are just not sure whether the best starting point is being an IDM. Teamwork has to be perfectly orchestrated as competition is tough.

As for the market share dynamics, the top 10 companies (IDMs) have been losing share. Fabless share has been growing, but it is still relatively small.

Coming to the realities of the foundry market, TSMC’s lead is now unassailable. Were it an IDM, it would be No. 2, challenging Intel and passing Samsung. Moving more into design looks inevitable.

Finally, execution, and not technology, is everything! Execution has and will continue to make the difference. Applications (software) will play the role of the key differentiator as well, and it has value. Design is the means to an end, and not the end.

From the chip industry’s perspective, the electronics market was traditionally Japan, North America and Western Europe. It now encompasses the entire Asian rim, China, Eastern Europe and India. Far from maturing, the chip industry itself is still in its volatile, high-growth phase, with at least a further 20 years of strong growth in prospect. Penn said, “The underlying growth drivers for chips has never been better.”

Back to basics
We started with the need to get back to industry basics. We end in the same way! Stick to basics like:

* Don’t invest in low cost areas just because they are cheap — they have a habit of becoming high cost tomorrow, plus the hidden extras.
* Don’t make outsourcing decisions just because they are easy — especially if there’s no way back.
* Don’t make strategic cut-backs just to trim the bottom line — some decisions, e.g., R&D, take a long time to impact, then it’s too late.
* Stop looking for high volume/high value market niches — they don’t exist, need to learn how to compete
* Do show strong leadership
* Do have a long-term plan and stick with it — even if it negatively impacts ‘the next quarter’ balance sheet
* Do show a commitment and determination to succeed
* Do stay focused and resistant to external meddling
* Do execute ruthlessly — this is the key competitive differentiator)
* Do … just do it with passion — it’s the passion that makes the difference

Encouraging developments in 22nm!

April 25, 2008 Comments off

Suddenly, but steadily, there seems to be lot of work going on in the 22nm space. This can only be encouraging for the global semiconductor industry.

Savor these! This week, SEMATECH researchers presented trend-setting research results in extending the CMOS logic and memory technologies at the International Symposium on VLSI Technology, System and Applications (VLSI-TSA), which ran from April 21-23, at Hsinchu, Taiwan.

According to SEMATECH, the new materials, processes and concepts discussed in a series of seven research papers describe how current semiconductor technologies can benefit from performance-enhancing features for future scaling needs.

The papers discuss leading-edge research into areas such as high-k/metal gate (HKMG) materials, flash memory, planar and non-planar CMOS technologies, including new finFET designs, which offer additional control on the channel or body of the device by using a controlling gate wrapped around a thin silicon “fin”.

Early this month, Chartered Semiconductor Manufacturing, one of the world’s top dedicated foundries, announced the extension of its joint development collaboration with IBM to include 22nm bulk complementary metal oxide semiconductor (CMOS) technology.

IBM and AMD have also been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003. In November 2005, the two firms announced an extension of their joint development efforts until 2011, covering 32nm and 22nm process technology generations. Intel has been working on 22nm for quite some time now.

And last July, PULLNANO, a project sponsored by the European Commission within the 6th Framework Program (FP6), reported several important results related to the future-generation 32nm and 22nm CMOS technology platforms, including the realization of a functional CMOS SRAM demonstrator built using 32nm design rules.

PULLNANO also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called ‘air gap’ technique.

Late last year, I attended a Semiconductor International Webcast, where one of the analysts, Carl Johnson of Research Infrastructure, had said that lot of consolidation was happening within the fab space. Mid-level players are consolidating. The customer base is clearly narrowing.

He said: “The cost of designing some of these leading-edge devices, and getting them to market, and then following it up with another product, if you don’t want to be a one-product guy, is a real challenge. That is limiting the number of players that are going into the mega fabs. So, the field is narrowing in 65nm, and 45nm, and as we get to below 45nm, the field is going to get much, much narrower.”

Perhaps, there will be fewer players after all, in the 22nm space. However, all of the encouraging developments mentioned above augur well for the semiconductor industry.

Challenges for IC industry and Dr. Gargini’s lessons

July 26, 2007 Comments off

Those who were fortunate enough to attend the recently held SEMICON WEST in San Francisco had the pleasure of attending a great session on the past. present and future challenges for the IC industry by Dr. Paolo Gargini, Director of Technology Strategy at Intel.

For those who may not have the time to read this article, here’s a snippet of what Dr. Gargini had to offer. The first lesson, he said, was that, “Something right may still happen even when everything seems to be going wrong.” However, challenges that were continuously posed also needed to be addressed at the earliest, in order to keep moving forward.

Many also predicted several times that some limit would be reached – that chip development would never get below ten nanometers, or below five nanometers. However, the industry was able to produce components with a gate oxide at about 1.2 nanometers.

Later, the game changed to scaling, which led to Gargini’s second lesson – “Predictors of engineering limits have always been proven wrong by the right improvements.” Shrinking silicon technology of the 1990s kept the industry moving forward.

His third lesson was, “It would be wrong to believe that the right fundamental limits don’t exist.” The fourth lesson was, “It is wise to look for the right solutions before things start going wrong.” Dr. Gargini recalled how Intel had announced that 45nm generation was ready. That it included high-k metal gates was only disclosed this January giving Intel the time to work on yields, enhancements, reliability problems, etc.

Gargini quoted Gordon Moore as saying that introduction of high-k metal gates was the single most important innovation in semiconductor manufacturing of the last 40 years!

Interestingly, a few weeks ago, the PULLNANO Consortium announced breakthrough results for 32nm/22nm. Among other things, the PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of transistors used in 45nm technology node.

These transistors are built using a low power consumption approach based on Fully Depleted Silicon On Insulator (FDSOI), coupled with a gate stack composed of a high-K gate dielectric and a single metal electrode stack. This is said to be the first time that such a compact SRAM cell has been fabricated using FDSOI, high-k dielectric and metal gate together.

Coming back to Dr. Gargini, his fifth lesson was, “It would be wrong to delay taking action and not do the right thing at the right time.” According to him, there was a need for re-examining the opportunities for reviewing “old” theories and techniques that didn’t work on silicon.

Paradigm shift indeed in semicon

July 11, 2007 Comments off

Going through an article written by Dr. Wolfgang Ziebart, Member of the Management Board, President and CEO, Infineon Technologies, in Financial Times Deutschland, one cannot help but appreciate the great paradigm shift that has indeed taken place in the semiconductor industry.

The article titled: A paradigm shift in the semiconductor industry: Could this be the end of Moore’s Law? focuses on how changing technologies are indeed making life difficult for most market players to keep pace with all those changes.

The technical possibilities for shrinking chips have far from reached their limits at 65nm. There are preparations already on for 45nm and development work for 32nm has already started!

When PULLNANO announced breakthrough results for 32/22nm, did it surprise many? The PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of transistors used in 45nm technology node.

It talks about a compact SRAM cell that has been fabricated using FDSOI (Fully Depleted Silicon On Insulator), high-k dielectric and metal gate all together.

PULLNANO has demonstrated that the material and integration schemes used in 45nm generation can be modified to provide a robust solution at 32nm. It has also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called ‘air gap’ technique.

I do remember Dr Pradip Dutta of Synopsys India telling me about two months ago about 32nm, during a course of a telephonic conversation about ndia’s moves in the semicon space.

After that conversation, I was wondering how quickly semicon technology had started to move. How quickly, from a has-been all these years, India was suddenly emerging as a semicon base to reckon with. How quickly, the geometry had moved from 90nm to, now, 22nm!

Dr Dutta also added that there would be more emphasis in India on doing high-end designs. In fact, whether it is frequency, number of gates, high complexity, etc., all of those would be driven by applications. India is now ready for doing high-end complex designs.

Indian companies are now definitely excelling in the design services sector. Some of them have also grown significantly. It is believed that they have also taken a load off the international design services company. Some of these Indian companies are now also developing their own IPs — a paradigm shift in itself!

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