Cadence Quantus solution meets 16nm FinFET challenges

Cadence Design Systems Inc. recently announced the Quantus QRC extraction solution had been certified for TSMC 16nm FinFET. So, what’s the uniqueness about the Cadence Quantus QRC extraction solution? KT Moore, senior group director – Product Marketing, Digital and Signoff Group, Cadence Design Systems, said: “There are several parasitic challenges that are associated with advanced

Cadence: Plan verification to avoid mistakes!

Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. 😉  I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification

Can 2014 be a major year for global semicon industry?

The year 2014 is expected to be a major year for the global semiconductor industry. The industry will and continue to innovate! Apparently, there are huge expectations from certain segments such as the so-called Internet of Things (IoT) and wearable electronics. There will likely be focus on the connected car. Executives have been stating there

How’s global semicon industry performing in sub-20nm era?

Early this month, I caught up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present. Performance in sub-2onm era First, let’s see how’s the global semiconductor industry performing after

Global semiconductor companies delivering platforms: Jaswinder Ahuja, Cadence

Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well and alive. The organization has been aligned around the EDA360 vision. The EDA360 is a five-year vision for defining the

Cadence Tempus accelerates timing analysis and closure by weeks!

Cadence Design Systems Inc. has announced the Tempus timing signoff solution. It facilitates ground-breaking signoff timing analysis and closure. The new technology accelerates timing analysis and closure by weeks. It is said to be up to 10X faster than competing solutions. Tempus has also been endorsed by Texas Instruments (TI). Complexity is growing exponentially and

Agnisys makes design verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient. Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip

Tensilica to expand Cadence IP footprint in SoCs

Tensilica DPU solutions are meant for broad applications. It is focusing on three key verticals — Hi-Fi audio voice, IVP imaging and Diamond controllers, as well as the Xtensa. Tensilica will expand the Cadence IP footprint in SoCs. This compliments Cadence and Cosmic Circuits interface and analog IPs. How does all of this fit into Cadence’s vision of

Tensilica acquisition to broaden Cadence’s IP portfolio

Last week (March 11, 2013), Cadence Design Systems Inc. entered into a definitive agreement to acquire Tensilica Inc., a leader in dataplane processing IP, for approximately $380 million in cash. With this acquisition, Tensilica dataplane processing units (DPUs) combined with Cadence design IP will deliver more optimized IP solutions for mobile wireless, network infrastructure, auto

Outlook for electronics and semiconductors in 2013

Happy new year to everyone! Here is an outlook for the electronics and semiconductors sectors in 2013, provided by Jaswinder Ahuja, corporate VP and MD, Cadence Design Systems (India) Pvt Ltd. (Thanks a lot, Pallavi). First, the past year, 2012, in review. Globally, 2012 has been a challenging year for the semiconductor industry with the economic