Are we about to reach end of Moore’s Law?

Here is the concluding part of my discussion with Sam Fuller, CTO, Analog Devices. We discussed the technology aspects of Moore’s Law and ‘More than Moore’, among other things. Are we at the end of Moore’s Law? First, I asked Fuller that as Gordon Moore suggested – are we about to reach the end of

STMicro intros M24SR dynamic NFC/RFID tag

STMicroelectronics recently introduced the M24SR dynamic NFC/RFID tag. Speaking about the USP of the M24SR, Amit Sethi, Product Marketing manager – Memories and RFID, STMicroelectronics India, said: “The unique selling proposition of the M24SR product is its two interfaces, giving users and applications the ability to program or read its memory using either an RF

How’s global semicon industry performing in sub-20nm era?

Early this month, I caught up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present. Performance in sub-2onm era First, let’s see how’s the global semiconductor industry performing after

SEMICON Europa 2013: Where does Europe stand in 450mm path?

SEMICON Europa was recently held in Dresden, Germany on Oct. 8-10, 2013. I am extremely grateful to Malcolm Penn, chairman and CEO, Future Horizons for sharing this information with me. SEMICON Europa included a supplier exhibition where quite a few 450mm wafers were on display. One highlight was a working 450mm FOUP load/unload mechanism, albeit

Great, India’s having fabs! But, is the tech choice right?

The government of India recently approved the setting up of two semiconductor wafer fabrication facilities in the country. It is expected to provide a major boost to the Indian electronics system design and manufacturing (ESDM) ecosystem. A look at the two proposals: Jaiprakash Associates, along with IBM (USA) and Tower Jazz (Israel). The outlay of

Higher levels of abstraction growth area for EDA

San Jose, USA-based Atrenta’s SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed. I recently met up with Dr. Ajoy Bose, chairman, president and CEO, Atrenta, to find out more. I started by asking how Atrenta

Moore’s Law could come to an end within next decade: POET

POET Technologies Inc., based in Storrs Mansfield, Connecticut, USA, and formerly, OPEL Technologies Inc., is the developer of an integrated circuit platform that will power the next wave of innovation in integrated circuits, by combining electronics and optics onto a single chip for massive improvements in size, power, speed and cost. POET’s current IP portfolio

What’s happening with 450mm: G450C update and status

The Global 450mm Consortium (G450C) has been driving the effective industry 450mm development. It is co-ordinating test wafer capability supporting development and demonstrating unit process tool performance. The focus is now on improving tools with suppliers to be ready for customer operations. Giving an update during the recently held Semicon West 2013 at San Francisco,

Moore’s Law good for 14nm, and probably, 10nm: Dr. Wally Rhines

Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute “Visionary Talk”, he found time to speak with me. First, I asked him given that the global semiconductor industry is entering the sub-20nm era, will it

Agnisys makes design verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient. Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip