How’s global semicon industry performing in sub-20nm era?

Early this month, I caught up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present. Performance in sub-2onm era First, let’s see how’s the global semiconductor industry performing after

Higher levels of abstraction growth area for EDA

San Jose, USA-based Atrenta’s SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed. I recently met up with Dr. Ajoy Bose, chairman, president and CEO, Atrenta, to find out more. I started by asking how Atrenta

Moore’s Law good for 14nm, and probably, 10nm: Dr. Wally Rhines

Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute “Visionary Talk”, he found time to speak with me. First, I asked him given that the global semiconductor industry is entering the sub-20nm era, will it

Global semiconductor companies delivering platforms: Jaswinder Ahuja, Cadence

Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well and alive. The organization has been aligned around the EDA360 vision. The EDA360 is a five-year vision for defining the

Cadence Tempus accelerates timing analysis and closure by weeks!

Cadence Design Systems Inc. has announced the Tempus timing signoff solution. It facilitates ground-breaking signoff timing analysis and closure. The new technology accelerates timing analysis and closure by weeks. It is said to be up to 10X faster than competing solutions. Tempus has also been endorsed by Texas Instruments (TI). Complexity is growing exponentially and

Semicon in sub-20nm era: Business as usual or different?

We are now entering the sub-20nm era. So, will it be business as usual or is it going to be different this time? With DAC 2013 around the corner, I met up with John Chilton, senior VP, Marketing and Strategic Development for Synopsys to find out more regarding the impact of new transistor structures on

Agnisys makes design verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient. Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip

Dr. Wally Rhines on global semiconductor industry trends for 2013

It is always a pleasure speaking with Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. I met him on the sidelines of the 13th Global Electronics Summit, held at the Chaminade Resort & Spa, Santa Cruz, USA. Status of global EDA industry First, I asked Dr. Rhines how the EDA industry was

Embedded software: Next revolution in EDA

There is a key lesson that Mentor Graphics made while trying to deliver solutions that were right for software and hardware developers. The lesson was: tailor the software to the discipline! Make it as similar to their environment as possible!! Delivering his speech at the ongoing 13th Global Electronics Summit in Santa Cruz, USA, Dr.

Tensilica acquisition to broaden Cadence’s IP portfolio

Last week (March 11, 2013), Cadence Design Systems Inc. entered into a definitive agreement to acquire Tensilica Inc., a leader in dataplane processing IP, for approximately $380 million in cash. With this acquisition, Tensilica dataplane processing units (DPUs) combined with Cadence design IP will deliver more optimized IP solutions for mobile wireless, network infrastructure, auto