According to Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics Corp., verification has to improve and change every year just to keep up with the rapidly changing semiconductor technology. Fortunately, the innovations are running ahead of the technology and there are no fundamental reasons why we cannot adequately verify the most complex chips and systems of the future. He was speaking at the recently held DVCON 2014 in Bangalore, India.
A design engineer’s project time for doing design has reduced by 15 percent from 2007-2014, while the engineer’s time for doing verification had seen 17 percent increase during the same time. At this rate, in about 40 years, all of a designer’s time will be devoted to verification. At the current rate, there is almost no chance of getting a single-gate design correct on first pass!
Looking at a crossover of verification engineers vs. designer engineers, there is a CAGR designers of 4.55 percent, and for CAGR verifiers, it is 12.62 percent.
The on-time completion remains constant, as we look at the non-FPGA project’s schedule completion trends, which are: 67 percent behind schedule for 2007, 66 percent behind schedule for 2010, 67 percent behind schedule for 2012, and 59 percent behind schedule for 2014. There has been an increase in the average number of embedded processors per design size, moving from 1.12 to 4.05.
Looking at the macro trends, there has been standardization of verification languages. SystemVerilog is the only verification language growing. Now, interestingly, India leads the world in SystemVerilog adoption. It is also remarkable that the industry converged on IEEE 1800. SystemVerilog is now mainstream.
There has been standardization in base class libraries as well. There was 56 percent UVM growth between 2012 and 2014, and 13 percent is projected growth in UVM the next year. Again, India leads the world in UVM adoption.
The second macro trend is standardization of the SoC verification flow. It is emerging from ad hoc approaches to systematic processes. The verification paradox is: a good verification process lets you get the most out of best-in-class verification tools.
The goal of unit-level checking is to verify that the functionality is correct for each IP, while achieving high coverage. Use of advanced verification techniques has also increased from 2007 to 2014.
Next, the goal of connectivity checking is to ensure that the IP blocks are connected correctly, a common goal with IP integration and data path checking.
The goal of system-level checking is performance, power analysis and SoC functionality. Also, there are SoC ‘features’ that need to be verified.
A third macro trend is the coverage and power across all aspects of verification. The Unified Coverage Interoperability Standard or UCIS standard was announced at DAC 2012 by Accellera. Standards accelerate the EDA innovation!
The fourth trend is active power management. Now, low-power design requires multiple verification approaches. Trends in power management verification include things like Hypervisor/OS control of power management, application-level power management, operation in each system power state, interactions between power domains, hardware power control sequence generation, transitions between system power states, power domain state reset/restoration, and power domain power down/power up.
Macro enablers in verification
Looking at the macro enablers in verification, there is the intelligent test bench, multi-engine verification platforms, and application-specific formal. The intelligent test bench technology accelerates coverage closure. It has also seen the emergence of intelligent software driven verification.
Embedded software headcount surges with every node. Clock speed scaling slows the simulation performance improvement. Growing at over 30 percent CAGR from 2010-14, emulation is the fastest growing segment of EDA.
As for system-level checking, as the design sizes increase emulation up, the FPGA prototyping goes down. The modern emulation performance nmakes virtual debug fast. Virtual stimulus makes emulator a server, and moves the emulator from the lab to the datacenter, thereby delivering more productivity, flexibility, and reliability. Effective 100MHz embedded software debug makes virtual prototype behave like real silicon. Now, integrated simulation/emulation/software verification environments have emerged.
Lastly, for application-specific formal, the larger designs use more formal. The application-specific formal includes checking clock domain crossings.
The EDA 360 was an industry vision. It reflected a change in market requirements. It was application driven system design. From a Cadence perspective, the company has done system design enablement, according to Nimish Modi, senior VP, marketing and business development, Cadence Design Systems Inc.
In Apple’s case, the iOS is unique. Cadence feels that the heart of the design is the SoC. The electrical analysis is becoming very important. For instance, how do you optimize before tape-out? Hardware and software conversion presents a huge problem as well. The IP plays an important part. Cadence did IP-as-a-service. It now has an IP strategy.
Today, EDA is about possibility, not productivity. Cadence provides tools and content for semiconductor and systems companies. It is now realizing the EDA 360 vision.
According to Modi, each IP is immensely complex. Standards based or interface IP is not enough! Silicon-proven design is the need of the hour. Now, more and more IP blocks are said to be coming together.
Cadence is offering the Palladium XP, and its primary use is for system verification. Software development is becoming a little bit difficult. People are providing software prototypes. The Palladium compile, turnaround and debug are very fast, best-in-class. All memory, clocking, partitioning, etc., is now automated.
The capacity of the Protium platform is 100 million gates. It will enable hardware and software developers. The use model for Protium is:
* Hardware folks use it for hardware regression.
* Software folks use it for early software development.
The main value proposition is the faster bring-up time. Also, the Palladium hybrid model helps customers overcome the boot problem. It is a hybrid of emulation and virtual prototyping. The dynamic power analysis is another issue. The Palladium hybrid model helps to do the testing.
Collaboration with ARM
ARM provides processor IPs. Cadence works closely with ARM. Cadence is also co-optimizing its tools to provide the best PPA. Physical libraries and tools get optimized. Cadence’s tools are optimized for ARM architecture. Cadence is also the first ones on the access to the V8 ARM models.
I had interacted with Dr. Ajoy Bose, CEO of Atrenta, some months ago. It was a pleasure to meet up with Piyush Sancheti, VP of Marketing recently. First, I asked him about the outlook for EDA in 2014.
Outlook for EDA
Piyush Sancheti said: “EDA does not look that attractive from growth point. However, you cannot do SoC designs without EDA. Right now, EDA’s focus is on implementation. The re-use of IP has been doing the rounds for many years. Drivers for SoCs are mobile and Internet of Things. The design cycle for those markets are very short – about three months. EDA business is shifting to IP re-use. The focus is now toward design aggregation.
“We will have done roughly 66 percent of business – net new — on existing customers. There is an industry shift toward doing more on the front end. EDA growth will come from IP-SoC involvement.
“Sub-20nm has challenges. ST says FT-SoI is the way to go. Complexity of process plays a big role, and the amount of chips you put in will also increase. In 14/16nm, we have an investment going on in 3D design. We are extending our 2D tool into 3D tool. We are also investing in the IP qualification. We have standardized a set of design rules in RTL. There are about 30 companies in the TSMC ecosystem.
“Our main focus is IP enablement. SoC acceptance is another key aspect. Our company focus is IP-enablement for SoCs. IP qualification ensures that it meets guidelines. Second, acceptance and making sure all IPs fit in the blocks. Third, integration. We already have this technology and it is driving the business.”
What’s Atrenta’s take on 3D design? Sancheti replied: “The industry has been slow as 3D designs are not yet to a point of business success. Focus on monolithic 3D-ICs will be a paradigm shift for the semicon industry. For mainstream commercial design, 20nm is still mainstream, but 14/16nm does not look mainstream, as of now. Process node is not necessarily a driver of innovation. EDA as an industry will remain in single digit growth.”
How will EDA move into the embedded software space?
Sancheti said: “We’ve looked into that market. But, the price point is significantly lower. Over time, it could be a strategic area for us. Over time, embedded software development and chip design will co-mingle.”
ESL is where the future of EDA lies. Still true? He added that the future of EDA is going up. It has to head toward integration of embedded software and chip development. However, ESL is not the only viable option.
Atrenta has 220 people in India, about 10 people in Bangalore and 200 in Noida. Sushil Gupta runs the India operations. It has tie-ups with IIT Delhi and IIT Kharagpur as well. Atrenta sees lot of scope for work with the Indian start-ups.
San Jose, USA-based Atrenta’s SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed. I recently met up with Dr. Ajoy Bose, chairman, president and CEO, Atrenta, to find out more.
I started by asking how Atrenta provides early design analysis for logic designers? He said: “The key ingredient is something we call predictive analysis. That is, we need to analyze a design at a high level of abstraction and predict what will happen when it undergoes detailed implementation. We have a rich library of algorithms that provide highly accurate ‘predictions’, without the time and cost required to actually send a design through detailed implementation.”
There’s a saying: electronic system level (ESL) is where the future of EDA lies. Why? Its because the lower level of abstraction (detailed implementation) of the EDA market is undergoing commoditization and consolidation. There are fewer solutions, and less differentiation between them. At the upper levels of abstraction (ESL), this is not the case. There still exists ample opportunity to provide new and innovative solutions.
Now, how will this help EDA to move up the embedded software space? According to Dr. Bose, the ability to do true hardware/software co-design is still not a solved problem. Once viable solutions are developed, then EDA will be able to sell to the embedded software engineer. This will be a new market, and new revenue for EDA.
How are SpyGlass and GenSys platforms helping the industry? What problems are those solving? Dr. Ajoy Bose said: “SpyGlass is Atrenta’s platform for RTL signoff. It is used by virtually all SoC design teams to ensure the power, performance and cost of their SoC is as good as it can be prior to handoff to detailed implementation.SpyGlass is also used to select and qualify semiconductor IP – a major challenge for all SoC design teams.
“GenSys provides a way to easily assemble and modify designs at the RTL level of abstraction. As a lot of each SoC is re-used design data, the need to modify this data to fit the new design is very prevalent. GenSys provides an easy, correct-by-construction way to get this job done.”
How does the SpyGlass solve RTL design issues, ensuring high quality RTL with fewer design bugs? He added that it’s the predictive analysis technology. SpyGlass provides accurate and relevant information about what will happen when a design is implemented and tested. By fixing these problems early, at RTL, a much higher quality design is handed off to detailed implementation with fewer bugs and associated schedule challenges.
On another note, I asked him why Apple’s choice of chips a factor in influencing the global chip industry? The primary reason is their volume and buying power. Apple is something of a “King Maker” when it comes to who manufactures their chips. Apple is also a thought leader and trend setter, so their decisions affect the decisions of others.
Finally, the global semiconductor industry! How is the global semicon industry doing in H1-2013? As per Dr. Bose: “We see strong growth. Our customers are undertaking many new designs at advanced process technology nodes. We think that this speaks well for future growth of the industry. At a macro level, the consumer sector will drive a lot of the growth ahead. For EDA, the higher levels of abstraction is where the growth will be.”
Today, EDA requires specialization. Elaborating on EDA over the past decade, Dr. Walden (Wally) C. Rhines, chairman and CEO, of Mentor Graphics, and vice chairman of the EDA Consortium, USA, said that PCB design has been flat despite growth in analysis, DFM and new emerging markets. Front end design has seen growth from RF/analog design and simulation, and analysis As design methodologies mature, EDA expenditures stop growing. He was speaking at Mentor Graphics’ U2U (User2User) conference in Bangalore, India.
Most of the EDA revenue growth comes from major new design methodologies, such as ESL, DFM, analog-mixed signal and RF. PCB design trend continues to be flat, and includes license and maintenance. The IC layout verification market is pointing to a 2.1 percent CAGR at the end of 2011. The RTL simulation market has been growing at 1.3 percent CAGR for the last decade. The IC physical implementation market has been growing at 3,4 percent CAGR for the last decade.
Growth areas in EDA from 2000-2011 include DFM at 28 percent CAGR, formal verification at 12 percent, ESL at 11 pecent, and IC/ASIC analysis at 9 percent, respectively.
What will generate the next wave of electronic product design challenges, and the future growth of EDA? This would involve solving new problems that are not part of the traditional EDA, and ‘do what others don’t do!
Methodology changes that may change EDA
There are five factors that can make this happen. These are:
* Low power design beyond RTL (and even ESL).
* Functional verification beyond simulation.
* Physical verification beyond design for manufacturability.
* Design for test beyond compression.
* System design beyond PCBs
Low power design at higher levels
Power affects every design stage. Sometimes, designing for low power at system level is required. System level optimization has the biggest impact on power/performance. And, embedded software is a major point of leverage.
Embedded software has an increasing share of the design effort. Here, Mentor’s Nucleus power management framework is key. It has an unique API for power management, enables software engineers to optimize power consumption, and reduces lines of application code. Also, power aware design optimizes code efficiency.
Functional verification beyond RTL simulation
The Verification methodology standards war is over. UVM is expected to grow by 286 percent in the next 12 months. Mentor Graphics Questa inFact is the industry’s most advanced testbench automation solution. It enables Testbench re-use and accelerates time-to-coverage. Intelligent test bench facilitates linear transition to multi-processing.
Questa accelerates the hardware/software verification environment. In-circuit emulation has been evolving to virtual hardware acceleration and embedded software development. Offline debug increases development productivity. A four-hour on-emulator software debug session drops to 30 minutes batch run. The offline debug allows 150 software designers to jumpstart debug process on source code. Virtual stimulus increases the flexibility of the emulator. As an example, Veloce is 700x more efficient than large simulation farms.
Physical verification beyond design for manufacturability
The Calibre PERC is a new approach to circuit verification. The Calibre 3DSTACK is the verification flow for 3D.
It is always a pleasure interacting with Dr. Walden (Wally) C. Rhines, the chairman and CEO, Mentor Graphics, and vice chairman of the EDA Consortium, USA. I started by enquiring about the global semiconductor industry.
Dr. Wally Rhines said: “The absolute size of the semiconductor industry (in terms or total revenue) differs depending on which analyst you ask, because of differences in methodology and the breadth of analysts’ surveys. Current 2012 forecasts include $316 billion from Gartner, $320 billion from IDC, $324.5 billion from IHS iSuppli, $327.2 billion from Semico Research and $339 billion from IC Insights.
“These numbers reflect growth rates from 4 per cent to 9.2 per cent, based on the different analyst-specific 2011 totals. Capital spending forecasts for the three largest semiconductor companies have increased by almost 50 per cent just since the beginning of this year. However, the initial spurt of demand was influenced by the replenishment of computer and disc drive inventories caused by the Thailand flooding. Now that this is largely complete, there is some uncertainty about the second half.
“So, overall it looks like the industry will pass $310 billion this year, but it may not be by very much. The strong capital spending and demand for leading edge capacity should impact the second half but the bigger impact will probably be in 2013.
What’s with 28.20nm?
Has 28/20nm semiconductor technology become a major ‘work horse’? What’s going on in that area? At least, this area is now of considerable interest.
Dr. Rhines said that the semiconductor industry’s transition to the 28nm family of technologies, which broadly includes 32nm and 20nm, is a much larger transition than we have experienced for many technology generations.
The world’s 28nm-capable capacity now comprises almost 20 per cent of the total silicon area in production and yet, the silicon foundries are fully loaded with more 28nm demand than they can handle. In fact, high demand for 28/20nm has created a capacity pinch that is currently spurring additional capital expenditure by foundries.
He added: “As yields and throughput mature at 28nm, the major wave of capital investment will provide plentiful foundry capacity at lower cost, stimulating a major wave of design activity. Cost-effective, high yield 28nm foundry capacity will not only drive increasing numbers of new designs but it will also force re-designs of mature products to take advantage of the cost reduction opportunity.”
Long-term trends are strong for semiconductor and electronics. According to databeans estimate (Feb. 2011), semiconductor revenue will likely reach $450 billion by 2015 and electronics revenuw will likely reach $2,800 billion by 2015.
Speaking at the CDNLive! 2011 event in Bangalore, India, Charlie Huang, SVP of Worldwide Field Operations, Cadence Design Systems Inc., said that the challenges in the near term are slowdown in Europe and USA. The weakness is driven by increasingly negative views on the global economy, end demand, orders and outlook. Key indicators are also showing that the economy is facing headwinds. The 2011 GDP growth projections have deteriorated since the beginning of the year. The economy has been marred by high unemployment and low consumer confidence.
As of now, innovation has been driving growth. Apps have been driving innovation, followed by video, mobility, cloud and green technology. The impact on the electronics industry is multi-fold. There is a new development paradigm and collaboration has been increasing. The IP is also expanding beyond cores and the EDA is changing.
The new development paradigm for system companies is to differentiate on applications and semiconductor companies must deliver on application-driven hardware-software platforms. IP has now expanded well beyond the core. EDA is also changing, and Cadence is investing to deliver on the EDA360 vision. There are multiple silicon realization challenges. Cadence silicon realization solutions enable fast, deterministic, end-to-end path to silicon success.
As an example, ARM and Cadence have collaborated on the GHz implementation of Cortex-A15. ARM chose ARM Artisan physical IP, evaluated the Cortex-A15 RTL, and supported CPF. Cadence optimized the EDA flow, experienced support at EAC, and provided EDA tool releases and iRM.
ARM, TSMC and Cadence also collaborated on the industry’s first 20nm Cortex-A15. TSMC provided the 20nm process qualification and A15 learnings. ARM handled the 20nm implementation experience, A15 considerations in 20nm and TSMC 20nm readiness milestone. Cadence provided the 20nm research to reality, contributed and grew the A15 expertise and TSMC 20nm readiness milestone.
The end result: the industry’s first 20nm Cortex-A15 tapeout, thanks to a successful three-way vertical collaboration. ARM, Cadence and TSMC engineers worked side-by-side. The project priorities included 20nm DPT implementation schedule and 20nm readiness milestone.
Great! That’s what was required!! As though software piracy isn’t enough, there is now an article about EDA software piracy!!!
According to the article, the anti-piracy committee of the Electronic Design Automation Consortium (EDAC) estimates that 30-40 percent of all EDA software use is via pirated licenses. That’s a huge number!
What are the chief reasons for EDA software piracy? Surely, it can’t be attributed to the Far East countries alone, and definitely not China and Taiwan, and perhaps, India, for that matter.
Everyone in the semiconductor industry knows that EDA software is required to design. There are hefty license fees involved that companies have to pay.
Designing a chip is a very complex activity and that requires EDA software. EDA firms send out sales guys to all over the country. Why, some of the EDA vendors are also known to form alliances with the technical colleges and universities. They offer their EDA software to such institutes at a very low cost.
Back in 2006, John Tanner wrote an article in Chip Design, stating: EDA tools shouldn’t cost more than the design engineer!
However, how many of such EDA licenses are properly used? Also, has the EDA vendor, who does go out to the technical institutes made a study about any particular institute’s usage of the EDA tool?
The recently held Design and Automation Conference (DAC) showered praises on itself for double-digit rise in attendance. Was there a mention of EDA piracy in all of that? No way! If so, why not?
The reasons are: the EDA industry already churns out a sizeable revenue from the global usage of EDA software. EDA firms are busy trying to keep up with the latest process nodes and develop the requisite EDA tools. New products are constantly being developed, and so, product R&D is a continuous event! Of course, in all of this race, EDA firms are continuously looking to keep their revenues running high, lest there is an industry climb-down!
Where then, are the reasons for EDA firms to even check, leave alone, control piracy?
An industry friend had this to say regarding EDA software piracy. “It is the inability to use certain ‘tool modules’ only at ‘certain time’. Like, if a IP company wants to just run PrimeTime (Synopsys) few times to ensure its timing worthiness before releasing that IP, and doesn’t need it after that. However, it is is not possible to get such a short time license.” Cost and unethical practices by the stake holders were some other reasons EDA users have cited.
Regarding the status in India, especially, the difference isn’t that much, from say, China. Another user said it is not such a prevelant, ‘worrisome’ aspect, yet. Yet another EDA user said that EDA piracy is there more in the sense of ‘unauthorized’ usage than ‘unpaid’ usage — not using it for what it is supposed to be used for. For instance, using academic licenses for ‘commercial developments’, etc.
That leads to the key question: can EDA software piracy be curtailed to some extent? One user feels that yes, it can. Perhaps, Microsoft type ‘detection’ technologies exist. However, another said that the EDA companies’ expenses have to do, so it can be more than actual losses. Hence, they are probably not quite doing it!
The Design and Automation Conference (DAC) 2011, kicked off today in San Diego, USA, with its usual slew of announcements. Leading the pack were Magma Design Automation and Cadence Design Systems, along with Synopsys, Mentor Graphics, and several others.
Magma Design Automation Inc. announced a partnership with Fraunhofer Institute for Integrated Circuits IIS to develop process-independent Titan FlexCell models of the Institute’s analog intellectual property (IP) cores. It also announced the availability of a netlist-to-GDSII reference flow for GLOBALFOUNDRIES’ 28nm super low-power (SLP) high-k metal-gate (HKMG) technology.
Magma announced the immediate availability of the Titan Analog Design Kit for TSMC 180nm and 65nm processes, that implements Titan’s model-based design methodology with Titan FlexCells, which are modular, process- and specification-independent, reusable analog building blocks.
Magma Design Automation also launched Silicon One, an initiative to bring focus to making silicon profitable for customers by providing differentiated solutions and technologies that address business imperatives facing semiconductor makers today – time to market, product differentiation, cost, power and performance.
Silicon One’s initial focus is on five types of devices that are key to electronic products that are most prevalent today:
* ASIC /ASSP
* Analog/mixed-signal (AMS)
* Processing cores
Cadence Design Systems Inc. isn’t far behind either! It announced an array of new technologies incorporated into the new TSMC Reference Flow 12.0 and AMS Reference Flow v2.0 that ensure 28nm production readiness. Cadence also announced a close collaboration with TSMC that will extend its interface IP offering. With Imec, in Belgium, Cadence announced a new technology that delivers an automated test solution for design teams deploying 3D stacked ICs (3D-ICs).
Cadence also announced the immediate availability of verification IP (VIP) for ARM’s new AMBA 4 Coherency Extensions protocol (ACE), extending its popular VIP catalog and speeding the development of multiprocessor mobile devices. Cadence further outlined the technologies and steps required to move the industry to advanced node design, with a particular focus on 20nm and 28nm design.
Mentor Graphics announced that the Catapult C high-level synthesis tool now supports the synthesis of transaction level models (TLMs). It also announced a unified embedded software debugging platform, from pre-silicon to final product, based on the integration of the Mentor Embedded Sourcery CodeBench embedded software development tools with Mentor’s leading electronic system level (ESL), verification, and hardware emulation products. These include the Mentor Graphics Vista Virtual Prototyping product, Veloce hardware emulator, prototype target boards, and end products or any combination thereof.
Mentor Graphics announced support for 3D-IC in TSMC’s Reference Flow 12.0 (RF12). Solutions for both silicon interposer and through silicon via (TSV) stacked die configurations are now supported by the Calibre physical verification and extraction platform and the Tessent IC test solution.
ARM and Synopsys Inc. have signed an expanded multi-year agreement extending ARM’s access to Synopsys’ innovative EDA technology. ARM will also provide Synopsys with access to the ARM Cortex-A15 processor to maximize performance and energy efficiency of SoCs built by ARM’s Partners using this advanced ARM processor and Synopsys tools. Read more…