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Top 10 captivating moments in Indian semicon during 2008

December 13, 2008 Comments off

Yes, the time has come for all of us to say goodbye to this year. It has been a very captivating year for the Indian semiconductor industry. Some consider it to be a year the industry came of age, while some others would look at the year as one where fab promises failed India.

Nevertheless, as I’ve maintained, having or not having a fab won’t affect India very much as its traditional strengths have been in embedded and design services.

There have been several moments during the year that I personally savor. In fact, I have either witnessed most of those or written/blogged about them.

The top 10 captivating moments in Indian semiconductors during 2008, according to me, are:

1. S. Janakiraman, former chairman, ISA, declared before the world, in May at Dubai, during the IEF 2008, about India’s growing strength in global telecom.

2. Growing interest in the solar photovoltaic industry in India, and subsequent proposals made by various companies, including Reliance.

3. EDA companies, such as Magma and also Synopsys, making their entry, or at least, intentions known, in the solar/PV industry.

4. Intel’s new chip, designed largely in Bangalore, and of course, the Intel Developer Forum in Taipei, Taiwan.

5. Visit of a strong Japanese delegation to Bangalore, which showed remarkable keenness regarding possible investments in India.

6. BV Naidu quitting SemIndia, and putting in doubt India’s fab story. Well, that’s a different story, and one person’s exit would not mean much to such a large industry.

7. ISA Excite, and the minister announcing that Karnataka could have its own semiconductor policy. The policy should be out in the new year, hopefully.

8. AMD’s new chip, the Shanghai, which again, had a lot of involvement from AMD’s Bangalore team.

9. NXP India achieving RF CMOS in a single chip. The entire analog and RF work was done in Bangalore, India.

10. Go parallel or perish, said James Reinders, of Intel! Parallelism or parallel computing involves the simultaneous use of more than one computer or processor to execute a program.

I was also present during the launch of Synopsys’ Galaxy Custom Designer, which tackles the analog mixed-signal (AMS) challenges. It would occupy a joint 10th position.

There may have been some other moments as well! Would like to hear from all of you what are those other great times in India semiconductor industry during 2008!

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Mentor on EDA trends and solar/PV

September 24, 2008 Comments off

This is a continuation of my recent discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

There have been whispers that the EDA industry has been presently lagging behind semiconductors and is in the catch-up mode. “That’s a matter of perspective. There are definitely unsolved challenges at 32nm and 22nm, but the reality is that we are still in the technology development stage,” he says.

For EDA tools that address implementation and manufacturing issues (i.e., Mentor design-to-silicon products), there are dependencies that cannot be fully resolved until the process technology has stabilized. Mentor Graphics is laying the groundwork for those challenges and working in concert with the process technology leaders to ensure that our products address all issues and are production-worthy before the process technology goes mainstream.

On the other hand, although Mentor’s products are fully-qualified for 45nm, there have only been a handful of tapeouts at that node, so for the majority of customers, we are ahead of the curve.

On ESL and DFM as growth drivers
ESL and DFM are said to be the new growth drivers. Sawicki adds: “As Wally Rhines has said in his public presentations, system level design and IC implementation are the stages of development where there are the most challenges, and therefore the most opportunities. To continue the traditional grow spiral that the electronic industry has enjoyed as a result of device scaling, we need more sophisticated EDA solutions to deal with both of these challenges.”

ESL is responding to the growth of design complexity and the need for earlier and more thorough design verification, including low power characteristics, and software integration.

The Design-to-Silicon division is addressing the issues of IC implementation which result not only from the increase in design complexity and devices sizes, but also from increasing sensitivity of the manufacturing process to physical design decisions, a phenomenon often referred to as “manufacturing variability.”

Although the term “Design-For-Manufacturing” reflects the need to consider manufacturability in design and to optimize for both functional and parametric yield, it is important to emphasize that DFM is not simply an additional tool or discrete step in the design process, but rather an integration of manufacturing process information throughout the IC implementation flow.

With single threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out. It would be interesting to see how is Mentor handling this.

According to Sawicki, Mentor has incorporated sophisticated multi-threading and multi-processing technologies into all of its performance-sensitive applications, from place-and-route, through physical verification, resolution enhancement and testing.

He says, “Our tools have a track record of impressive and consistent and performance and scalability improvements, which is why we continue to lead the industry in performance.”

In addition to merely adding multi-threading and support for multi-core processors, Calibre products have a robust workflow management environment that automatically distributes the processing workload in the most efficient manner across any number of available clustered computing nodes.

Mentor’s Olympus-SoC place-and-route is inherently scalable due to its advanced architecture which includes an extremely efficient graph representation for timing information, and a very concise memory footprint. In addition, all the engines within Olympus-SoC can take advantage of multi-threaded and multi-core processors for high performance. These features enable Olympus-SoC to handle 100M+ gates designs in flat mode without excessive turnaround time.

Mentor’s ATPG tools are also designed to operate in multiprocessing mode over the multiple computing platforms to reduce test pattern generation time. In addition, Mentor test pattern compression technology reduces test pattern volume and test time, making it feasible to fully test 100M gate devices and maintain product quality without an explosion in test cost.

With EDA is starting to move up to the system level, will this make EDA less dependent on the semiconductor world?

Sawicki agrees that there are challenges at both the front end and back end of the electronic products design and manufacturing life cycle. Both of these opportunities are growing. In addition, developments like multi-level (3D) die packaging, through-silicon via (TSV) structures and other non-traditional techniques for device scaling are pushing system and silicon design issues closer together.

Reaching the 22nm node will require highly compute intensive EDA techniques for physical design to compensate for limitations in the manufacturing process. Beyond that, we could see a major shift to new materials and manufacturing techniques that would open new green fields for EDA in the IC implementation flow.

EDA going forward
How does Mentor see the EDA industry evolving, going forward?

Sawicki adds: “There are three key trends to watch. Firstly, for design to remain affordable at the leading edge, we need to enable radical increases in productivity. Electronic System Level (ESL) design is the key here, allowing designers to move to a new level of abstraction for both design and verification.

“Secondly, the challenges of manufacturing a well-yielding and reliable device as we move to 22nm will require a far more sophisticated physical implementation environment—one that accounts for physical effects in the design loop, and accounts for manufacturing variability in it’s optimization routines.

“Finally, the manufacturing challenges also open significant opportunity for EDA in the manufacturing space. A great example of this is the September 17, 2008 announcement we did with IBM on a joint development program to enable manufacturing at the 22nm node.”

Finally, given the roles already defined by Magma and Synopsys in solar, is there an opportunity for EDA in solar/PV?

According to Sawicki, as the photovoltaic devices have very simple and regular structures, most of the opportunity for EDA is not in logic design tools, but in material science, transistor-level device modeling, and manufacturing efficiencies with a focus on conversion efficiency and manufacturing cost reduction.

EDA’s role in solar will be in the newer areas related to Design-for-Manufacturing and other manufacturing optimizations, he concludes.

Our last discussion on DFM will follow in a later blog post!

Synopsys’ Dr Chi-Foon Chan on India, low power design and solar

September 11, 2008 1 comment

There have been reports about the troubles within the EDA industry in recent times, especially those related with quarter sales. Interestingly, Synopsys has been the one sailing along fine! If that’s not enough, it made its intention known of playing a role on the solar/PV segment, an area where lot of investments have been happening!

Given this scenario, I was fortuitous enough, rather, extremely lucky to be able to get into a conversation with Dr. Chi-Foon Chan, President and Chief Operating Officer, Synopsys Inc., during his recent visit to India.

On the state of the global semiconductor industry, he said, it was somewhere now in the low 10s [well below 10 percent]. The EDA industry is currently tracking below that level. However, Synopsys has been growing at around 10 percent. He said, “The technology challenges today are very high.”

Synopsys has a substantial number of R&D population based out of India. Giving his assessment of the Indian semiconductor industry, Dr. Chan added: “Our main interest in India is largely talent and the academia. India can very well get more into the product development side. Even the outsourcing of designs have increased. Our capabilities, of the Indian team, have also increased.”

As with any good semiconductor ecosystem, the Indian industry also needs a proactive industry association, a role played to near perfection by the ISA (India Semiconductor Association). Acknowledging the ISA’s role, Dr. Chan said, “The ISA has also formed a very cohesive team.”

There is little doubt about India’s growing importance in technology strengths and managerial leadership. Dr. Chan added: “We are more on the high-end side and also track what others design. In India, the profiles of designs are definitely high-end in nature. This is largely due to the presence of a large number of MNCs. A very high percentage of designs are in the 45nm and 65nm process technology nodes.”

There is another significant indicator of India’s growing importance, and that is the huge rise in the attendance of the SNUG. In 2000, this event attracted 180 people. However, in 2008, the SNUG attracted over 2,000 people.

Moving India to next level
Given the very high level of commitment on Synopsys’ part toward India, there was a need to find out from Dr. Chan what exactly India needs to do to move to the next level in the value chain in the semiconductor ecosystem.

He advised: “India can do two to three things. One, for the system to grow, you need the government, academia and industry to grow together. India has all of the ingredients required to drive products.”

Comparing India with China, he highlighted the fact that while in China, the local consumption was higher than local supply, that was not the case with India!

“Therefore, looking at merely the local market is not the only thing. Products developed here can also be targeted at the Middle East and Southeast Asia.” He was quite forthright in his analysis, adding: “Industries start when you find markets. The skill sets are already present here. There can well be multiple startups.”

Dr. Chan also touched upon the fab vs. fabless issue, noting that there could well be more of fabless companies in India. “Building a fab requires lot of capital. Also, consolidation will continue to happen.”

What role does Dr. Chan see Synopsys playing in the Indian context? He said: “Synopsys will continue to be a catalyst for the industry. A healthy design industry in India continues to help us. We also work well with the Indian universities. Having more people from the universities will always help. We also invest a lot in application support. The application team also trains others. I now look forward to seeing more fabless companies here and India to become even more global.”

On low power design
India is also a centre of expertise in low power design, given that low power is hugely important in today’s electronics ecosystem. Dr. Chan commented that low power has always been the number one design issue. It cannot be taken care of at one single stage.

He added: “A slightly new concept that has emerged is low-power verification. There are so many schemes for attacking low power, such as multiple voltage islands. We (Synopsys) are spending a lot of effort in low power.

“As a designer, you require detailed analysis. Low-power verification is now coming up. Another area is testing. As an example, if so much power is required, how do you have the power cut from the tool you are using to test? From a Synopsys point of view, we are involved in several points, such as front-end synthesis, testing, sign-off, verification, etc. We are trying to put in a whole lot of methodologies.”

Synopsys in solar
EDA may be able to help by lowering power requirements and leakage on better products. Especially, the Synopsys’ TCAD product can be used to create more efficient and effective solar cells. Now, this is not a new development anymore. Synopsys, along with Magma, have already made known their intentions about setting foot in the solar/PV space.

On the TCAD, Dr. Chan said: “We have a very strong position in the TCAD, commercially. Now, it is one of our most critical elements in high-performance. Our TCAD is among the strongest in the EDA industry.

“In solar, it does not have to be a complicated place-and-route, etc. From an entire solar industry point of view, we have now used some effort from TCAD into this space. Heat transfer issues, etc., are more in the EDA space.”

I will continue my conversation with Synopsys on its solar initiative sometime later. Keep watching this space, folks

Magma’s YieldManager could make solar ‘rock’!

September 10, 2008 Comments off

Make no mistake, folks! The EDA guys are getting their act together to penetrate the solar/PV segment!! Magma’s YieldManager is a great example of that effort! Yes, we all know the troubles of the EDA industry as well as of the key players. However, let’s not ignore this initiative from Magma!

Recently, Magma Design Automation Inc. announced the development of a new yield enhancement software system, the YieldManager software system, which is customized for solar fabs to improve conversion efficiency, increase yield and reduce the manufacturing costs of solar cells.

Magma is collaborating with Pegasus Semiconductor-Solar to refine the product specifications and test the new product, based on Magma’s YieldManager.

This is an interesting development, especially from the point of view of the solar/PV industry! Even more significant is the entrance of the EDA community [the one being Synopsys] into solar/PV, a segment, which has witnessed a substantial amount of investments worldwide, and specifically, in India.

It was fun catching up with Ankush Oberai, VP, Failure Analysis Business Unit, Magma Design Automation, in Silicon Valley, to find out more about the YieldManager software system, what it can do for the solar/PV industry, and why Magma decided to venture into an ‘unchartered territory’.

The first and most obvious thing, why YieldManager?

Ankush Oberoi says that in semiconductors, yield impacting parameters which are regularly monitored are mostly extrinsic, i.e., from outside, such as particles, over-exposure, under-exposure and miss-processing. In solar cells, the yield impacting parameters are mostly intrinsic, that is, something built into the solar cell material which can NOT be easily seen. Thus, a different “eye” is needed to see the solar parameters. The “eye” is the YieldManager here!!!

It would NOT be either inspection tools or litho optical proximity correction (OPC) detector. The solar cell efficiency is directly influenced by electro-physics of solar materials. A YieldManger is required to monitor any changes in those efficiency impacting parameters.

The most important parameter is the lifetime of current-generating carriers. As the solar energy generates the “hole-electron” pairs, they are collected separately as electricity.

If the solar material is “dirty” with many crystalline boundaries as in thin film solar cells, the solar generated hole-electrons get pulled into those crystalline boundaries and do not contribute to the electricity generation.

“Thus, if we can find a solar yield management system to detect the very subtle change in carrier lifetime, then we are at home with a greatest Home Run in solar cell business,” he contends.

Given the EDA background, why did Magma decide on a yield management technology?

He adds that yield management technology was acquired by Magma as part of the Knights Technology acquisition in Nov 2006. Magma’s Fab Business Unit (formerly, Knights Technology) is a pioneer (since 1994) in yield management for semiconductor technology.

The product is deployed and used in leading fabs around the world to help manage production wafer yield. Yield management has also been deployed for mask making and LCD productions.

It would be interesting to know how Magma’s new product will allow solar fabs to better monitor all metrology, inspection and performance data throughout the manufacturing process.

Oberoi says: “For Si wafer solar cell, the most important parameter to monitor is the solar conversion efficiency impacting parameters. An example would be a carrier lifetime.

“If the carrier lifetime fluctuates more than normal, the solar Yield Manager will quickly examine all of the key data, i.e., metrology, inspection and performance data, to pinpoint out potential root-causes of the fluctuation problem.”

For thin film solar cell, particles, laser cutting integrity and film thickness uniformity would be main things to monitor. Those data are quite similarly collected, as in semiconductors, and would be monitored as similar ways. The Solar Yield Manager would do well as proven in semiconductors in this case.

Next, it is important to find out how will the YieldManager enable fab operators to identify and correct root causes of solar-efficiency and yield degradation caused by subtle fab processing fluctuations or instability.

According to Oberoi, the carrier lifetime, which could be caused by various factors, is the most critical parameter to monitor for achieving and maintaining the good solar conversion efficiency.

He says: “As the Solar Yield Manager carefully monitors those factors, blindly committing ~400,000 wafers a day can be eliminated, when critical process instability starts appearing and persists. The solar conversion efficiency impacting factors could be monitored differently by different solar fabs.”

Some fabs may not have capabilities to monitor those factors. The Solar Yield Manager would define those metrology and performance tool requirements, when released.

It is also interesting to learn how improving the energy conversion efficiency, reducing the manufacturing costs and increasing the yield of silicon wafer-based solar cells are critical to the growth of the solar market.

Currently, the Si wafer for solar cell costs $2~$2.5/watt due to the severe shortage of Si. The selling price of a solar cell is $3~$3.5/watt, that is, the material cost is 60~70 percent of the solar cell price.

No market or industry would prevail with the 60~70 percent material cost, adds Oberoi. Thus, every milli-watt squeezed out of a solar cell would be very critically important for proliferation of solar industry.

In order to increase the power output of a solar cell, the solar conversion efficiency must be maximized. Once maximized, sustaining the good solar efficiency is the name of the game in the solar cell manufacturing business.

The effective manufacturing cost will be drastically lowered, if bad solar cells with poor solar efficiency is minimally produced. That is, some fabs will use ~400,000 wafers a day to generate ~500 M-Watt a year, whereas some ~450,000 wafers to do the same with poorer solar efficiency.

Innovation in the solar fabrication process must be accelerated, and today, no other enterprise-wide yield enhancement software exists for solar fabs.

Oberoi says: “Solar cell is an old technology, but a very new industry, simply because not enough money was being invested. Now, money is pouring into the solar industry and products like solar Yield will start to appear. It is not known yet that anyone commercially has tried to develop a similar product.”

Global estimate of solar/PV industry
There are several publications with recent estimates. The annual solar cell installation in the world: Germany ~46 percent, Japan ~23 percent, USA ~9 percent, Spain ~6 percent, Italy ~4 percent, the rest of Europe ~1 percent, the rest of Asia, including India and China ~6 percent, and the rest of world ~5 percent in 2006.

Magma is currently in the design and implementation stages of the product and plan to have version 1.0 of the product commercially available in Q1-09. The company has targeted solar fabs based in Asia that are eager for early implementation of the solar yield product.

Right then: those planning or having solar fabs! Now’s the time to test that home run theory with the YieldManager.

On possible Samsung-SanDisk deal; AMD’s fab-lite path

September 6, 2008 Comments off

Last week, the global semiconductor industry has been hearing and reading about two big speculative stories:

a) A possible acquisition of SanDisk by Samsung, and
b) A possible chance of AMD taking the fab-lite route.

First on Samsung’s buyout (possible) of SanDisk! There have been rumors of a possibility of Samsung acquiring SanDisk. While it is still a possibility, it also leads to several interesting questions!

Should this deal happen, what will be the possible implications for the memory market? Will this also lead to a possible easing off on the pricing pressures on the memory supply chain? And well, what happens to the Toshiba-SanDisk alliance?

A couple of weeks back, iSuppli, had highlighted how Micron had managed to buck the weak NAND market conditions, and was closing the gap with Hynix in Q2, and that NAND recovery was likely only by H2-2009.

I managed to catch up again Nam Hyung Kim, Director & Chief Analyst, iSuppli Corp., and quizzed him on the possible acquisition of SanDisk by Samsung.

A caution: Remember, all of this is merely based on speculation!

On the possibility of Samsung’s takeover of SanDisk, he says: “Samsung at least said that they consider it. Thus, it is a possible deal. But who knows!”

Kim is more forthright on the implications for the memory market, should this deal happen, and I tend to agree with him.

Consolidation inevitable; no impact on prices
The chief analyst quips: “The NAND flash market is still premature and there are too many players in flash cards, USB Flash drives, SSD, etc. The industry consolidation should be inevitable in future.”

So, will this possible buyout at least ease some pricing pressures on memory supply chain? “I don’t expect this deal to impact the prices. Prices will depend on suppliers’ capacity plans. In the memory industry, the consolidation has never impacted the prices in a long run. (maybe, just a short-term impact). As you know, Micron acquired Lexar a few years ago, but no impact,” he adds.

Is there any possibility of SanDisk delaying its production ramps and investments at two of its fabs? And, what will happen should it do so?

Nam says: “SanDisk has already said that they would delay its investment and capacity plan given difficult market condition. This is a positive sign to the market as we expect slower supply growth than expected in future. However, in a long run, consolidation won’t impact the market up and down.”

Negative impact likely for Toshiba?
Lastly, what happens to the SanDisk-Toshiba alliance, should the Samsung buyout of SanDisk does happen?

Nam adds: “It is negative to Toshiba. The company [Toshiba] not only loses its technology partner, but also loses its investment partner. It should be burden for Toshiba to keep investing themselves to grow its business.”

Well, in SEMI’s Fab Forecast Report, there is mention of how Toshiba and SanDisk are among the big spenders in fabs, in Japan. Considering that Japanese semiconductor manufacturers are more cautious, it would be interesting to see how this deal, should it happen, affects the Toshiba-SanDisk alliance.

Now, AMD goes fab-lite?
While on fabs, this brings me to the other big story of last week — of AMD going the fab-lite route, possibly!

Magma’s Rajeev Madhavan had commented some time back that fab-lite is actually good for EDA. It means more design productivity. Leading firms such as TI, NVIDIA, Broadcom, etc., are Magma’s customers.

Late last year, Anil Gupta, MD, India Operations, ARM, had also commented on some other firms going fab-lite! Gupta pointed out Infineon, NXP, etc., had announced Fab-Lite strategies. Even Texas Instruments was moving to a Fab-Lite strategy. “IDMs are going to be the fabless units of today and tomorrow,” he added.

So much for those who’ve taken the fab-lite route, and industry endorsements.

On the fab-lite subject, iSuppli’s Kim will not speculate whether AMD would actually break up into into two entities: design and manufacturing, and also prefers to wait and watch.

How does fab-lite actually benefit? He comments: “Fab-lite has not been working well in the memory industry, which requires very tight control. It works, IF two companies (an IDM and a foundry) work very closely. For example, the industry leader, Samsung, produces all of the memory alone without any foundry relationship.”

Watch this space, folks!

Staying ahead of clock a habit at Magma!

April 2, 2008 Comments off

EDA is a complex industry to be in, what with process geometries changing all the time and EDA firms compelled to keep up with those changes. Magma Design Automation Inc. has been one of those, which has kept ahead of the changes and also managed good growth. In other words, Magma has managed to beat the clock consistently and stayed ahead, and continues to do so.

According to Rajeev Madhavan, chairman and CEO, Magma Design Automation Inc.. Magma has been outperforming the EDA industry by 2x globally. He touched upon the drive toward consumerization. Whle it was driven by PCs during the 1980s, mobile phones and PDAs are now the growth drivers for the common man. The consumer space is driving semiconductor applications as well. These are in form of devices with smaller form factors, where power is an important issue.

As an example, Madhavan highlighted the fact that 75 percent of the chips in the iPhone type of complex cell phone has been done using Magma. “We enable such points to happen. Consumer applications are driving EDA, and we are providing that change.”

According to him, India is a major center for Magma. An entire business line of products are now being driven out of India. The physical verification units – DRC, etc., — are all done here. Magma is consistently developing new products and product lines. Any MNC in India has an opportunity to build relationships with the EDA powerhouse.

EDA is all about integration. With operating margins getting slimmer, most companies have been moving to Fab-Lite. India has great expertise in design knowledge. India should shift its focus on developing the intellectual knowledge side, contended Madhavan. As for fabs, as and when those happen in India, they will definitely create jobs. “Fab-lite is actually good for EDA. It means more design productivity. Leading firms such as TI, NVIDIA, Broadcom, etc., are our customers,” he said.

Magma is now looking at more value addition and faster development. It has covered the entire EDA domain. Magma has a culture of rewriting its software a lot more and also covers all new process geometries. According to Madhavan, Magma is constantly in touch with leading foundries such as TSMC.

It is said that right now, around 75 percent of the chips in 45nm currently use Magma. Magma is also working with a customer in 32nm. Madhavan said: “You have to develop the tools as the processes change. At Magma, we need smart people who can understand electrical engineering and computer science. Growth comes in identifying and building the talent pools.”

As for product lines developed in India, Magma’s Quartz Formal has been developed largely in India. Most of the development work is happening in NOIDA, near Delhi. Work on DRC is being done out of Bangalore. “Every single product from Magma has some footprint in India,” he said. The complexities of chips have been growing and those require more automation.

Magma intends to grow from $178 million to $211 million during 2008. Madhavan felt that as the eco-system units come up in India, the company can move forward. Magma is hopeful that more design companies will be getting into India.

90nm designs major in India
Ricky Bedi, Senior Director, Application Engineering, Magma Design Automation India Pvt Ltd, added that the EDA industry had moved on from being optimizers. India too has to now move forward from being outsourcers to enablers.

He said, “When that happens, India will play a bigger role and offer more services. For example, Wipro, etc., are now doing full turnkey solutions.” Magma India is now working with over 32 universities, regional engineering colleges (RECs), IITs, etc. The intent is to facilitate VLSI programs in all of those places.

However, he agreed that the innovation has not really kicked off in the country. As of now, 90nm designs are in the majority in India, and in comparison, 65nm designs are lesser. Magma has already gone into 45nm, and even into 32nm. Bedi said: “Right now, yield is imperative in 45nm. Innovation will continue in the smaller geometries. Innovation has to focus more on predictability, etc.”

There is another trend worth mentioning — about re-usable IPs. According to Magma, there will be even more of re-usable IPs. As the designs themselves get complex, designers need to achieve those in shorter timeframes as the time-to-market (TTM) is crucial. Replication of blocks is also happening. Implementation of re-usable IPs will go up a notch, added Bedi.

While the EDA tools are now catching up with the advances in semiconductors, it has not been smooth sailing for language. Bedi added: “As far as language is concerned, language itself does not blend so easily. It takes great effort to move from Verilog to VHDL.”

Yatin Trivedi, director, Industry Partnership Program, Design Implementation Business Unit, Magma Design Automation Inc., touched upon the aspect of power. He said: “In the EDA format, it is important that the power format is accepted by as many vendors. The difference should be in the usage, not the format. In any design flow — from RTL to GDS — any design that is implemented must be simulated. Power information is now an integral part of the design. Leakage can destroy a die.”

Indian designers could lead in EDA product development

January 13, 2008 Comments off

There will be the multi-nationalization of the product development process, according to Walden C. Rhines, chairman & CEO, Mentor Graphics. More executives recognize that “access to qualified personnel” is the key driver. As per A.T. Kearney Global Services Location Index 2007, India is the most attractive offshoring destination. He was speaking at the Though Leadership Forum organized by the India Semiconductor Association.

Touching on the evolution of EDA, and the role of Indian designers, Rhines said that most electronic engineers did not consider themselves “risk takers”. Most electronic engineers also don’t like to change tools and fewer even consider “hot” new tools.

On the contrary, young engineers and recent university graduates eagerly adopted new technology. It is a way for them to distinguish themselves, get the productivity advantage and they were less invested in existing methodologies.

Indian designers smart
Comparing Indian designers with the rest of the world, he said that electronic designers in India, on an average, are less experienced than in the United States, Europe and Japan. However, they are on an average, as smart, or smarter, than those in United States, Europe and Japan. There has been an increasing influence of India design centers on the multinational design flows and tools.

Disruptive change creates leadership opportunities. There has been improved power and cost through improved system architecture. The C synthesis enables faster architectural exploration and shorter time to Verilog.

C synthesis matches or exceeds hand coded RTL efficiency, as per STMicroelectronics (Reed-Solomon, Galois Field Multiplier). There have also been system architectural innovations to reduce die size — Ericsson mobile platforms. There is a need to iterate to find the optimum architecture.

Now, Indian designers have been early adopters of C-based design. The reasons were, one there was a willingness to try new approaches and two, it caused multinational parent companies to accelerate their own adoption.

India is likely to be a leader in transaction level design. They have been able to extract fast, accurate power and timing models from RTL. They have managed runs 100x-1000x faster vs. RTL, retained accuracy at the gate level and RTL, their models run with application software for hardware/software cosimulation, and they have done transaction-based verification using emulation. It has been the same for UPF-compatible verification.

Some other areas of verification where India may lead the way are assertions, coverage based verification, and algorithmic test bench synthesis.

Adoption of place and route technology
Let us see how the adoption of new place and route technology has influenced the industry. When a design flow breaks, what breaks the most often? Place and route breaks every two technology generations. Technology generations ramp to peak volume. Place and route utilizes a semiconductor company’s internal software until gate array routers emerge.

Cell-based layout requires hierarchical router with timing. Tangent attacks leading-edge 0.75 micron designs. Later, Cadence became the dominant place and route supplier at 0.35 micron as the fabless industry grew demand. [Cadence acquired Tangent in 1989]. However, at 0.25 microns, SoC drives new technology requirements. This led to the collapse of the FAM business model.

SoC needs “break” the flow. ArcSys emerged at 0.35/0.25 micron. It addresses SoC requirements for large sizes and interconnect delay. It goes public as Avant!, and is later acquired by Synopsys. However, a timing closure crisis emerges at 0.13 micron. Cadence and Avant!/Synopsys try to extend older tool architectures.

Now, timing closure “breaks” the design flow. At this point, Magma emerges at 0.13 micron with timing-driven layout solution. At 90nm, Magma dominates timing-driven design. It also approaches Cadence, Avant!/Synopsys place and route market share. What the industry witnesses is that a new problem emerges and a new, leading-edge solution provider enters every two nodes.

And now, pressures are creating 65/45nm discontinuity. These are process and design variations, low-power requirements, and large design data sizes. Explosive growth in complexity requires multi-corner, multi-mode analysis.

Achieving power/performance design goals requires analysis of corner cases for manufacturing and operational variability. Manufacturing variability multiplies the required corner cases. Hence, manufacturing variability now “breaks” the place and route flow at 65nm. With the advent of 45nm, it demands design for manufacturing (DFM), and ushers in more corners.

Implications for EDA in India
So what are the implications for EDA in this scenario, especially from an Indian context? One, introduce and support leading-edge design tools in India. Two, EDA startups will focus initial sales efforts in San Jose and India. Three, purchasing decisions will increasingly incorporate India design teams to drive flows and decisions. Four, India will emerge as the test bed for new design ideas. As a result, Indian designers would exercise their influence by demanding the best-in-class design tools and capabilities.

Indian designers should always remain open to new design approaches. They should beware of becoming risk adverse as they become more experienced. They should need to stay abreast of the emerging innovations by maintaining close contact with EDA companies, including start-ups. They also need to make EDA suppliers aware of their issues and challenges.

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