Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.
Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.
The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.
Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.
IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”
The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.
“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.
Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.
Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.
The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.
Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.
How is IDesignSpec working as chip-level assertion-based verification?
Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
Xilinx Inc. has announced solutions for significant and growing gaps in ASIC and ASSP offerings targeting next-generation smarter networks and data centers. It has been acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services that leverage Xilinx’s All Programmable FPGAs, SoCs, and 3D ICs.
To find out more about how are Xilinx’s solutions targeting growing ASIC and ASSP gaps for next-gen smarter networks and data centers, I spoke with Neeraj Varma, director, Sales-India, Xilinx. He said: “Over the past several years, Xilinx has been making a transition from the leading FPGA vendor to a provider of All Programmable Solutions for Smarter Systems. With its All Programmable 7 Series FPGAS, All Programmable SoCs and the VivadoTM Design Suite, Xilinx now offers a comprehensive set of solutions that provide end-to-end system implementation.
“Through strategic acquisitions, investments in silicon products and IP development, Xilinx has started to replace entire ASSPs and ASICs in the communications market by offering a complete IP cores portfolio which allows customers to design Smarter Systems for networking, communications and data center applications.
“Xilinx is calling this set of IP cores, SmartCORE IP, because they are the critical application-specific building blocks needed to develop smarter networking and communications systems. We are responding to market need and that need has accelerated recently as the viability of ASICs and more recently ASSPs have been severely challenged. Xilinx is a generation ahead in SoC and tools and its leadership at 28nm borne out with revenue ramp.”
Developing SmartCORE IP portfolio
What is meant by Xilinx acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services?
According to him, 28nm design process devices require a new and a different set of tools to exploit all the capabilities. That was one of the reasons for Xilinx to invest heavily in resources and time to come up with the Vivado Design Suite, to be able to support the large designs and get them into production with minimal effort and ease.
Vivado supports the growing use of IP blocks to reduce the complexity of the designs which are very critical in the implementation of complex networking and communications systems. This is one of the main reasons Xilinx spent years to develop strategic partnerships and making acquisitions such as Omiino (OTN IP solutions), Modelware (Traffic Management and Packet processing IP solutions), Sarance (Ethernet and Interlaken IP solutions) and Modesat (Microwave and Eband backhaul IP solutions) to offer a comprehensive set of IP cores to design Smarter Systems for networking, communications and data centre applications.
How are the solutions going to address the challenges with ASICs and ASSPs?
He said that ASICs and ASSPs targeting the communications, networking, and data center equipment markets have been disappearing at a surprisingly rapid pace due to many factors, including escalating IC-design costs and the need for much greater levels of intelligence and adaptability—all driven by wide variance in application and device requirements.
Additionally, the equipment markets no longer accept “me too” equipment design, which means that ASSP-based equipment design has almost vanished due to limited flexibility. These growing gaps are pervasive across all markets.These challenges, coupled with the rapidly increasing design costs and lengthy design cycles for both ASICs and ASSPs have created significant solution gaps for equipment design teams.
ASSPs and ASICs are either too late to market to meet OEM or operator requirements, are significantly overdesigned to satisfy the superset requirements of many diverse customers, are not a good fit for specific target applications, and/or provide limited ability for customers to differentiate their end products. Equipment vendors face many or all of these gaps when attempting to use the solutions offered by ASIC and ASSP vendors.
Last week, Xilinx discussed its Targeted Design Platforms, aimed at accelerating the development of system-on-chip (SoC) solutions with Xilinx Virtex-6 and Spartan-6 FPGAs.
I was in conversation with Brent Przybus, Director of Product Marketing, as well as Neeraj Varma, Country Manager, Sales, for India and Australia and New Zealand.
First up, the ISE Design Suite 11.2 is now available for download, with full public support for Virtex-6 and Spartan-6 FPGA families. Xilinx also introduced the Spartan-6 and Virtex-6 base evaluation kits, which can be order immediately by customers.
Since this is the ISE Design Suite 11.2, Przybus added that prior to June 24, support for the Virtex-6 and Spartan-6 FPGA families was available only to early access customers.
Accelerating development of SoC solutions
Next, the Base Targeted Design Platform is said to accelerate the development of SoC solutions. According to Przybus, the Base Targeted Design Platform provides a framework that customers can extend to build their SoC solutions.
“We are providing the common functions including host interface and external memory controller as well as multi-boot in a system configuration. Customers can leverage this code saving weeks of months of development.”
The obvious question, why this release now, and not earlier? According to Varma: “Xilinx has always had boards, silicon, tools, IP and reference designs. However, with changes in market conditions and customer needs evolving, what became abundantly clear in recent years is that we need a more formalized and efficient way of providing a base for customers to build upon. Customers have also been asking for more complete design solutions.”
The concept for Base Targeted Design Platform was introduced in February when Xilinx had announced the architectural details of Spartan-6 and Virtex-6 FPGA devices along with the entire targeted design platform strategy.
“When the announcement was made, we had early access customers designing with Spartan-6 and Virtex-6 FPGAs. With the release of the ISE Design Suite 11.2, we are opening up public access to the two new device families. By doing so, we are opening up access through software of all our new devices, we are also making technical documentation, user guides and other resources available to all customers,” he added.
The release of the Base Targeted Design Platform is coincidental to the public availability of software supporting both Virtex-6 and Spartan-6 FPGAs.
The new Virtex-6 FPGA and Spartan-6 FPGA Evaluation Kits are the first in a series of kits that Xilinx will offer throughout the year designed to simplify the evaluation and development of SoCs with the latest generation of programmable technologies from Xilinx.
Now that the first kits have been released, let us probe into Xilinx’s plan for evaluation kits that it will offer throughout the year.
Varma added: “According to our Targeted Design Platform strategy, we have introduced the first level of our offerings. Moving forward, throughout the year we will introduce the Domain Specific Platform and then the Market Specific Platform. The Domain Kits will incorporate embedded kits, connectivity kits, and finally the DSP kits for both Virtex-6 and Spartan-6.” This point should be noted with great care by designers as lots more is in the offing from Xilinx.
The Market Specific Platform will address specific markets and include Communication, Video and Broadcast Kits, Market specific IP, custom tools and custom boards, added Varma.
Spartan-6 SP601 evaluation kit
Xilinx also introduced the Spartan-6 SP601 evaluation kit. Brent Przybus highlighted that the Spartan-6 SP601 evaluation kit is designed to address customers developing high volume, lower cost applications.
He elaborated: “The kit features the Spartan-6 LX16 FPGA and ships with a full base reference design and interface software providing customers a host communications link, built-in memory controller core that interfaces to DDR2 DRAM on the SP601 board, support for multi-boot, and a processing block that enables customers to see and measure the benefits of using a hard IP vs. Logic only simple processing function.
Addressing defense, aerospace apps
How useful will be all of this for defense and aerospace applications? According to Neeraj Varma, a lot of aerospace and defense applications require high performance digital signal processing (DSP), for example, in their video processing, secure communications, wireless communications (software defined radio or SDR), etc.
“Using the Base Targeted Design PLtatform as shown in the demonstration video, designers will be able to evaluate tradeoffs in performance, precision, and power consumption using hard DSP slices available in Spartan-6 and Virtex-6 FPGAs,” he said.
Using the DSP slices in Spartan-6 will help designers boost their performance by five times with higher precision without resulting into the increase of overall power consumption.
Varma added: “The Base Targeted Platform that we have announced will help our customers tune their applications not only in the aerospace and defence applications, but can be used for other applications in different vertical markets as well. Through this year, we will introduce Domain Specific Kits followed by Market Specific Kits. The Market Specific Platform will further address the specific defense applications in future.”
Lastly, there has been a lot of focus on design re-engineering and design security.
Przybus pointed out that the specific reference design shown in the Xilinx demo video has been done in HDL and doesn’t include and design security.
“The base reference design is portable and can be extended in a number of ways. The customer could use the built-in features like DeviceDNA, AES encryption of bitstream, etc. in our Virtex-6 and Spartan-6 silicon to secure their designs,” he noted.
Altera has developed the industry’s first low power FPGAs with anti-tamper, design security, and design separation. Extending low-power leadership, these low power FPGAs offer double the resources for less than 0.25W!
The Cyclone III LS devices offer up to 200K LEs for less than 0.25W of static power. It is said to be targeting power- and board-space-sensitive applications in all market segments. “Any market that requires low power and security features will require this product,” said Ms Susan Chang, AP marketing manager for Cyclone Series, Altera, underlining the growing importance of low-power FPGAs into power-constrained applications. The devices are shipping to customers now.
A closer look at the Cyclone III LS FPGAs reveals the following:
Low power: 200K LE (logic elements) for under 0.25W; TSMC 60nm low-power (LP) process; and Quartus II software power-aware design flow.
* Information assurance design suite: Offering data protection for information-assurance applications, features include anti-tamper, design security, design separation and IP, design examples, etc.
* High functionality: Featuring densities ranging from 70K to 200K LEs; up to 8.2 Mbits of embedded memory; and up to 396 embedded multipliers.
The Cyclone III LS FPGAs are said to have the most comprehensive IP protection in an FPGA. It protects the IP with anti-tamper and design security. “There is a JTAG port protection to prevent reverse engineering,” Chang added.
Security features include CRC to monitor for configuration changes, zeroizing the device if tampering is detected, and an on-chip oscillator that acts as an uninterruptible clock source for system monitoring.
Design separation features include single-chip redundancy and supporting information-assurance applications. This leads to reduction in power and board space, as well as reduction in BOM (bill of materials) cost — by about 50 percent.
Yet another feature is that of data assurance with design separation. Designers can now create physically isolated partitions with design separation. This protects against time-dependent faults and SEU, and increases the system uptime as well. These enable achieving a higher level of integration on a single device.
Military market and SDR
According to Chang, the military market will be among the most important ones for these devices. Hence, Altera’s clear thrust on design security and prevention of reverse engineering!
Focusing on the size, weight, and power (SWaP), these will support next-generation SDR waveforms with small footprint and low power (e.g., MUOS, SRW), night-vision goggles, and secure communications. It features crypto-modernization moving toward standardization.
The Cyclone III LS devices also support existing SDR (software-defined radio) applications. Chang said that SDR is one common design trend in the military market.
The next-generation software-defined radio (SDR) waveforms require more memory and logic for networking in the field and low power for extended battery life. Some other key requirements include small footprint for board space, data security for multiple channels in a single chip, and IP security and anti-tamper.
As far as the next-generation SDRs are concerned, these devices will facilitate reduction of the overall board space by up to 50 percent, an increase in the battery life by up to 2X, besides facilitating a single-chip secure SDR solution.
This is said to be the industry’s first FPGA design solution with fully interoperable domain-specific design flows and user-specific configurations for logic, digital signal processing (DSP), embedded processing, and system-level design.
The ISE Design Suite 11.1 release is a major milestone in the delivery of targeted design platforms with simpler, smarter design methodologies for creating FPGA-based system-on-chip solutions targeting a wide variety of markets and applications.
Tom Feist, Senior Marketing Director, Xilinx Inc., said that the company has been driving the evolution of FPGA design with domain-specific development environment for targeted design platforms. The new ISE Design Suite 11.1 sets the industry standard for delivering FPGA design tools and intellectual property (IP) to embedded, DSP and logic designers.
“This is a series of announcements that Xilinx is working on. We are releasing the IC Design Suite 11, for now,” he added. “Target design platform is a focus for Xilinx right now. We are working with Vita Consortium — Vita 57.” This is the FPGA I/O Mezzanine Card (FMC) standard, which aims to bring modularity to FPGA designs.
Meeting diverse requirements of FPGA design teams
Tailored for domain-specific methodologies, Xilinx’s ISE Design Suite 11 has four configurations aligned to user-specific methodologies — logic (VHDL/Verilog), embedded, DSP, or system design. It has the FLEXnet license management to better meet the design teams’ needs.
It also delivers methodologies specific to each designer’s needs. Each configuration delivers domain specific tools and IP, and accelerates designer productivity. The Suite narrows the focus to design differentiation, and not the design flow. Besides, it leverages the robust ecosystem of third party partners.
“The goal is to build a strong foundation with the targeted deisgn platform. Each edition of the Design Suite includes all of the tools/IPs needed to create, validate and implement,” Feist added.
“We are introducing four different versions — one for the logic designers; one for the embedded designers, one for the DSP desgners; and for system integrators,” he said.
“The overall strategy is to increase designers’ productivity. To drive this to the next level, we look at the development phase of our customers. FPGA design teams face different requirements. We need to provide methodologies that are working for each one of the individuals,” Feist added. The goal being — for each new tool, provide the IP and help validate the design.
More turns/day for designers
Overall, there are improvements for all designers, leading to more turns per day. There are improvements in the place-and-route algorithms. It delivers an average of 2X faster runtimes. The second generation SmartGuide provides an additional 2X improvement. The Design Suite also supports multi-threaded place and route.
Other improvements include: XST delivers an average of 2X faster synthesis runtime; improved support for SecureIP provides faster simulation PowerPC, MGT, and PCI hard IP blocks — supports Mentor, Cadence and Synopsys simulators; 10 percent better dynamic power via place and route optimizations; and reduction of memory requirements by an average 28 of percent.
Feist clarified: “The 2X improvement in implementation is compared to 10.1, our previous release. The 2X improvement related to SmarGuide is relative to a full re-implementation. Also, the 10 percent better dynamic power via place-and-route optimizations is against the previous release.”
The Xilinx ISE Design Suite has been positioned as a key enabler for targeted design platforms. It delivers optimized tool flows for each member of the design team. Thereby, it aims to boosts user productivity, improve quality of results, accelerate time to production, and enable designers to focus on differentiation.
Who would be the main users — power or mainstream? Feist said: “This will be useful for power users as well. Even the pushbutton users will still need to do pin layout. We have tried to make this very intuitive. You can look at the different levels.”
Nearly 17 months ago, I’d discovered FPGA Central! This discovery has gone one better — introducing the FPGA Seek (www.fpgaseek.com)!
According to the site, the FPGA Seek is a search engine optimized for field programmable gate array (FPGA) and CPLD’s related topics. FPGA Seek brings together the search engine technology from Google but with a laser focus on results related to FPGA/CPLD.
This search engine only goes on to show the importance FPGAs have been gaining. Even the open source world hasn’t been far behind. Recently, Altera’s Nios II processor received Wind River Linux support. And just before that, both Xilinx and Altera chose to release products the same day!
FPGA related jobs
Of course, there’s a whole lot of information on this site. Users can also suggest a site they’d like to be added. There’s also a link to FPGA and CPLD related jobs. Of course, it opens on to the FPGA Job Central page. In fact, a lot of jobs have been posted in the recent days. So, those looking for openings, do check it out.
I’ve been also conducting several searches on the site and am delighted to find several references to my articles/blog posts. 🙂
Enough said… perhaps, you should all check out and bookmark FPGA Seek! Lastly, thanks to FPGA Central for letting me know!!
Hardly any segment of the global semiconductor industry has escaped the economic financial crisis! Nevertheless, as the year draws to a close, several segments are planning strategies for tackling what could well be a difficult 2009! FPGAs are no exception!
Jennifer Lo, Senior Marketing Manager, Altera Asia Pacific, agrees. Highlighting the impact, as per reports in the media, the economical environment we are getting into is extremely challenging. Recently, Gartner lowered its 2009 semiconductor forecast to ‘down 16 percent’ as compared to 2008.
Altera placed strongly
Lo says that compared to the other semiconductor companies, many of whom are taking very drastic measures in cutting down costs and preserving capital, Altera is in a very strong position, both financially and product-wise.
Financially, Altera is said to have taken steps to focus on cost reductions and simplification internally, a few years ago. The company is seeing great results from those efforts. “You may check our financial data and find that we are essentially debt-free and have very healthy balance sheet. We continue to be profitable even under the very challenging environment we are in,” Lo contends.
Product-wise, Altera announced a few days ago that it is shipping the industry’s 40nm product, considered a key milestone. “We are very excited about it with this new product family, Stratix IV, which offers the industry’s largest density, highest performance, highest system bandwidth and lowest power, targeting customers in a variety of markets, including communications, broadcast, test, medical and military,” she says.
Going forward in 2009, Altera will continue to rollout the rest of the members in the Stratix IV product family. It will also continue to execute new product strategies in the plan with full confidence.
Tackling demand weakness in FPGAs
There have been whispers regarding demand weakness in the FPGA industry. On the contrary, Lo adds that lower power, lower cost and smaller space are still common needs for portable applications for 2009. These needs may drive PLD vendors to focus on architecture and process to address power and cost. Also, work on package to develop a smaller device. Altera’s goal is to still focus on these common needs.
The Altera MAX II Z already offers the lowest dynamic power and comparable static power in industry already. The company may focus more on package size on 2009.
Although leading-edge FPGAs are scaling to 40nm and beyond, have the tools caught up with these new and complex processes? She says that lowering power consumption and improving customer productivity have been the focus of Altera’s product strategies for the past few years.
Lo adds: “Lowering power consumption means lowering costs for customers, not only in the BOM cost (reducing heatsink or cooling requirement), but also the ongoing operating cost (fans, air-conditioning costs,…etc). At this day and age of ever increasing fuel and electricity costs, this is gaining significance in customers’ selection consideration. Seeing such a need, reducing device power consumption has been a major element in the company’s product planning and execution.”
Altera’s Max II Z product in the low-cost CPLD line offers the lowest dynamic power and static power in the industry that is catered for the portable applications. On the high end of the spectrum, with Stratix IV GX, for example, with the advanced 40nm process node, Altera utilizes the ‘Strained Silicon’ technology, lower core voltage of 0.9V, triple gate oxide, as well as low-K inter-metal dielectric material low power transceiver designs.
“In terms of design, we put in extra effort in lowering the overall power consumption in the transceivers as well as optimized DDR memory interfaces,” she notes.
Coupled with programmable power technology, which allows customers to use high performance (hence, high power consumption) circuitry for design along the critical path, while either using low-power circuit on other parts of the design or turning the logic blocks completely off while not in use, all process and design innovations work together toward one common goal of lowering the overall power consumption in the customer design.
Lo says: “In customer productivity improvement, we’ve invested in the feature sets in our design software, Quartus II, to enable team-based designs, incremental compilation, as well as faster compilation time compared to the other competing software. We also have a wide suite of IPs in a multitude of applications and technologies, such as our Nios embedded processors, the many memory interfaces and peripherals. Combining all of those with our SOPCBuilder tool also enables customers to integrate system designs with very much reduced time and effort.”
There have also been some talks lately about FPGA design starts being quite flat over the last couple of years.
Altera sees a lot of new market applications for FPGAs, apart from the traditional communications market. Out of the many market segments that it participates in, the company feels that communications, military and industrial segments will be in better situation than others in the next couple of years. Needless to say, Altera will continue to focus on these segments.
Tackling complexity is a major focus area for projecting FPGAs as a growth segment for 2009.
Lo says: that as with other previous downturns, the industry may go through its reformation, which may inevitably involve some weaker companies to either go out of business due to deteriorating business environment or get acquired by stronger companies. Altera is very confident that programmable logic, with its highly flexibility, versatile application, will have a good market position in 2009.
The Hardcopy ASIC is said to have been Altera’s major differentiator from the other PLD/FPGA vendors.
“We are the only company having both an FPGA vehicle to enable fast time-to-market and simultaneously possessing the seamless migration platform to low-cost production support using Hardcopy ASIC. With the industry trend of fewer and fewer ASIC starts due to the high NRE costs and high justifying volume, there will also be less investment in the ASSP front given the contracting demand. We see Hardcopy as a major competitive edge that will us bring to a different rank in the industry,” she notes.
Indeed, it is good to see companies thinking very hard about tackling a difficult 2009! There’s lot of fight left, and it’s not that semiconductor companies haven’t faced downturns earlier. Keep the faith and allow these folks to come up tops again!