Pick video IP as close as to "plug-and-play" for SoC integration

While designing, it is critical to pick the appropriate codec or formats that can be handled by a video IP to support any given application. It is also very important to select the correct video IP with proper and standard interfaces so that it can be as close as possible to ‘plug-and-play’ in terms of

Accelerating EDA innovation through SoC design methodology convergence

According to Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics Corp., verification has to improve and change every year just to keep up with the rapidly changing semiconductor technology. Fortunately, the innovations are running ahead of the technology and there are no fundamental reasons why we cannot adequately verify the most complex chips and

SEMICON Europa 2014 calls for innovators

SEMICON Europa 2014 will be held at Grenoble, France, on October 7-9 October, 2014. The event will see over 400 exhibitors, which means, the exhibition area has expanded by over 40 percent vs. 2013. There will be over 70 programs featuring 300+ speakers. SEMI expects 6,000+ visitors. A feature of the event will be the

Innovating in system of systems: Lip Bu-Tan

There have been several innovations of innovations happening in the global technology industry. The IoT, mobility, cloud computing, etc., are creating opportunities for the system of systems, according to Lip-Bu Tan, president and CEO, Cadence Design Systems Inc. Tan was delivering the main keynote. at the recently held CDNLive 2014 in Bangalore, India, Some of

How Intel competes on today’s fabless ecosystem?

The SEMI/Gartner Market Symposium was held Semicon West 2014 at San Francisco, on July 7. Am grateful to Ms. Becky Tonnesen, Gartner, and Ms Agnes Cobar, SEMI, for providing me the presentations. Thanks are also due to Ms Deborah Geiger, SEMI. Dean Freeman, research VP, Gartner, outlined the speakers: • Sunit Rikhi, VP, Technology and

Set up strong methodology teams to create better verification infrastructure: Synopsys

This is the third installment on verification, now, taken up by Synopsys. Regarding the biggest verification mistakes today, Arindam Ghosh, director – Global Technical Services, Synopsys India, attributed these as: * Spending no time on verification planning (not documenting what needs to be verified) and focusing more on running simulations or on execution. * No

Cadence: Plan verification to avoid mistakes!

Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. 😉  I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification

Are we about to reach end of Moore’s Law?

Here is the concluding part of my discussion with Sam Fuller, CTO, Analog Devices. We discussed the technology aspects of Moore’s Law and ‘More than Moore’, among other things. Are we at the end of Moore’s Law? First, I asked Fuller that as Gordon Moore suggested – are we about to reach the end of

3D remains central theme for Applied in 2014!

Following a host of forecasts for 2014, it is now the turn of Applied Materials with its forecast for the year. First, I asked Om Nalamasu, senior VP, CTO, Applied Materials regarding the outlook for the global semicon industry in 2014. Semicon outlook 2014 He said that Gartner expects the semiconductor industry to grow in

FinFETs delivering on promise of power reduction: Synopsys

Here is the concluding part of my conversation with Synopsys’ Rich Goldman on the global semiconductor industry. Global semicon in sub 20nm era How is the global semicon industry performing after entering the sub 20nm era? Rich Goldman, VP, corporate marketing and strategic alliances, Synopsys, said that driving the fastest pace of change in the