According to Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics Corp., verification has to improve and change every year just to keep up with the rapidly changing semiconductor technology. Fortunately, the innovations are running ahead of the technology and there are no fundamental reasons why we cannot adequately verify the most complex chips and systems of the future. He was speaking at the recently held DVCON 2014 in Bangalore, India.
A design engineer’s project time for doing design has reduced by 15 percent from 2007-2014, while the engineer’s time for doing verification had seen 17 percent increase during the same time. At this rate, in about 40 years, all of a designer’s time will be devoted to verification. At the current rate, there is almost no chance of getting a single-gate design correct on first pass!
Looking at a crossover of verification engineers vs. designer engineers, there is a CAGR designers of 4.55 percent, and for CAGR verifiers, it is 12.62 percent.
The on-time completion remains constant, as we look at the non-FPGA project’s schedule completion trends, which are: 67 percent behind schedule for 2007, 66 percent behind schedule for 2010, 67 percent behind schedule for 2012, and 59 percent behind schedule for 2014. There has been an increase in the average number of embedded processors per design size, moving from 1.12 to 4.05.
Looking at the macro trends, there has been standardization of verification languages. SystemVerilog is the only verification language growing. Now, interestingly, India leads the world in SystemVerilog adoption. It is also remarkable that the industry converged on IEEE 1800. SystemVerilog is now mainstream.
There has been standardization in base class libraries as well. There was 56 percent UVM growth between 2012 and 2014, and 13 percent is projected growth in UVM the next year. Again, India leads the world in UVM adoption.
The second macro trend is standardization of the SoC verification flow. It is emerging from ad hoc approaches to systematic processes. The verification paradox is: a good verification process lets you get the most out of best-in-class verification tools.
The goal of unit-level checking is to verify that the functionality is correct for each IP, while achieving high coverage. Use of advanced verification techniques has also increased from 2007 to 2014.
Next, the goal of connectivity checking is to ensure that the IP blocks are connected correctly, a common goal with IP integration and data path checking.
The goal of system-level checking is performance, power analysis and SoC functionality. Also, there are SoC ‘features’ that need to be verified.
A third macro trend is the coverage and power across all aspects of verification. The Unified Coverage Interoperability Standard or UCIS standard was announced at DAC 2012 by Accellera. Standards accelerate the EDA innovation!
The fourth trend is active power management. Now, low-power design requires multiple verification approaches. Trends in power management verification include things like Hypervisor/OS control of power management, application-level power management, operation in each system power state, interactions between power domains, hardware power control sequence generation, transitions between system power states, power domain state reset/restoration, and power domain power down/power up.
Macro enablers in verification
Looking at the macro enablers in verification, there is the intelligent test bench, multi-engine verification platforms, and application-specific formal. The intelligent test bench technology accelerates coverage closure. It has also seen the emergence of intelligent software driven verification.
Embedded software headcount surges with every node. Clock speed scaling slows the simulation performance improvement. Growing at over 30 percent CAGR from 2010-14, emulation is the fastest growing segment of EDA.
As for system-level checking, as the design sizes increase emulation up, the FPGA prototyping goes down. The modern emulation performance nmakes virtual debug fast. Virtual stimulus makes emulator a server, and moves the emulator from the lab to the datacenter, thereby delivering more productivity, flexibility, and reliability. Effective 100MHz embedded software debug makes virtual prototype behave like real silicon. Now, integrated simulation/emulation/software verification environments have emerged.
Lastly, for application-specific formal, the larger designs use more formal. The application-specific formal includes checking clock domain crossings.
IoT gathering pace as revolution: Guru Ganesan
By 2020, there will be over 8 billion people on our planet. This will also bring tremendous innovations and challenges. ARM has been connecting intelligence at every level, said Guru Ganesan, president and MD, ARM India.
He was delivering the guest keynote at the recently held CDNLive 2014 event in Bangalore, India.
Newer apps are helping connect with the world. As per Gartner, $27 billion worth apps were downloaded in 2013. By 2020, this is estimated to rise to $80 billion.
According to Ganesan, consumer trends are driving innovation in embedded apps, including rich user interface (UI). ARM is also at the heart of wearable technologies, for example, Smart Glasses from Google. Some examples from India include Lechal from Ducere Technologies, GOQ Pi remote fitness companion, Fin+ navigation and device control gesture based device from RHLVision, and Smarty Ring that brings instant smartphone alerts to your fingers from Chennai.
So, what are the key requirements for wearables? These are video/image, audio, display, software, OS, connectivity and battery life! In 2013, over 1 billion smartphones were shipped. Further, mobile data 12 times over between now and 2018.
In medical electronics, besides humans, it has extended to keeping the cattle healthy and have intelligent agriculture with OnFarm, by using sensors. IoT as a revolution is gathering pace. As per a survey conducted by ARM, 95 percent of the users expect to be using IoT over the next three years. Common standards are being developed for interoperability. Similarly, mobility and connectivity are also happening in automotives.
Now, let’s see the development challenges for high-end embedded. Embedded applications today integrate more functions. Consequently, design and verification challenges continue to grow. Further, lot of smart devices are now generating lot of data. The question is: how are we using that data?
Ganesan added that by 2020, there will be new challenges in transportation, healthcare, energy and education. Once devices start communicating with each other, we are likely to see the evolution of a smart infrastructure.
There have been several innovations of innovations happening in the global technology industry. The IoT, mobility, cloud computing, etc., are creating opportunities for the system of systems, according to Lip-Bu Tan, president and CEO, Cadence Design Systems Inc.
Tan was delivering the main keynote. at the recently held CDNLive 2014 in Bangalore, India,
Some of the trends driving the global semiconductor market growth in the end markets include automotives at $24 billion, computers at $76 billion, industrial electronics at $14,1 billion, medical electronics at $12.5 billion, and mobile phones at $100 billion. In India, especially, a lot of fabless companies are said to be coming up.
The tablet is a system of systems. It has communications, navigation, recording and photography, etc. Even the automotive vehicle is a convincing example. Next, there is the IoT. There are said to be diverse needs for the IoT.
There are said to be several challenges for the system of systems. Some of these are more IP and software requirements, and more needs for low power and mixed signal. System design enablement requires system integration, packaging and board, etc.
Cadence has a comprehensive SoC IP solution. The mixed signal verification solution ensures functionality, reliability and performance. Cadence also introduced the Voltus-Fi custom power integrity solution in Shanghai the week before. Its Quantus QRC extraction solution gives up to 5X performance.
Next, the Jasper acquisition expands the Cadence development suite. Cadence also provides the FPGA-based prototyping with Palladium flow for software development.
Tan concluded that new technologies always require closer collaboration — from IP through manufacturing. Cadence is here to help designers innovate — from systems to silicon.
Cadence Design Systems Inc. recently announced the Quantus QRC extraction solution had been certified for TSMC 16nm FinFET.
So, what’s the uniqueness about the Cadence Quantus QRC extraction solution?
KT Moore, senior group director – Product Marketing, Digital and Signoff Group, Cadence Design Systems, said: “There are several parasitic challenges that are associated with advanced node designs — especially FinFET – and it’s not just about tighter geometries and new design rules. We can bucket these challenges into two main categories: increasing complexity and modeling challenges.
“The number of process corners is exploding, and for FinFET devices specifically, there is an explosion in the parasitic coupling capacitances and resistances. This increases the design complexity and sizes. The netlist is getting bigger and bigger, and as a result, there is an increase in extraction runtimes for SoC designs and post-layout simulation and characterization runtimes for custom/analog designs.
“Our customers consistently tell us that, for advanced nodes, and especially for FinFET designs, while their extraction runtimes and time-to-signoff is increasing, their actual time-to-market is shrinking and putting an enormous amount of pressure on designers to deliver on-time tapeout. In order to address these market pressures, we have employed the massively parallel technology that was first introduced in our Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution to our next-generation extraction tool, Quantus QRC Extraction Solution.
“Quantus QRC Extraction Solution enables us to deliver up to 5X better performance than competing solutions and allows scalability of up to 100s of CPUs and machines.”
Support for FinFET features
How is Quantus providing significant enhancements to support FinFET features?
Parasitic extraction is at the forefront with the introduction of any new technology node. For FinFET designs, it’s a bit more challenging due to the introduction of non-planar FinFET devices. There are more layers to be handled, more RC effects that need to be modeled and an introduction of local interconnects. There are also secondary and third order manufacturing effects that need to modeled, and all these new features have to be modeled with precise accuracy.
Performance and turnaround times are absolutely important, but if you can’t provide accuracy for these devices — especially in correlation to the foundry golden data — designers would have to over-margin their designs and leave performance on the table.
How can Cadence claim that it has the ‘tightest correlation to foundry golden data at TSMC vs. competing solutions’? And, why 16nm only?
According to Moore, the foundry partner, TSMC, asserts that Quantus QRC Extraction Solution provides best-in-class accuracy, which was referenced in the recent press announcement:
“Cadence Quantus QRC Extraction Solution successfully passed TSMC’s rigorous parasitic extraction certification requirements to achieve best-in-class accuracy against the foundry golden data for FinFET technology.”
FinFET structures present unique challenges since they are non-planar devices as opposed to its CMOS predecessor, which is a planar device. We partnered with TSMC from the very beginning to address the modeling challenges, and we’ve seen many complex shapes and structures over the year that we’ve modeled accurately.
“We’re not surprised that TSMC has recognized our best-in-class accuracy because we’re the leader in providing extraction solutions for RF designs. Cadence Quantus QRC Extraction Solution has been certified for TSMC 16nm FinFET, however, it’s important to note that we’ve been certified for all other technology nodes and our QRC techfiles are available to our customers from TSMC today.”
Intersolar North America successfully concluded its seventh annual show in the heart of the United States’ largest solar market, California. More than 17,000 visitors from 74 countries visited 530 exhibitors.
The show had the latest innovations in the photovoltaic, energy storage, balance of systems, mounting and tracking systems, and solar heating and cooling market sectors.
It just shows how the USA has evolved as a leading market for solar PV over the years. One could feel USA creeping up on China! Which brings me to the other significant news.
Recently, there was news regarding the USA-China solar dispute. USA has won huge anti-dumping tariffs in the US-China solar panel trade case. A preliminary decision by the US Department of Commerce has imposed significant tariffs on Chinese solar modules in the anti-dumping portion of the case.
The decision has also closed SolarWorld’s “loophole,” which is said to have allowed Chinese module manufacturers to use Taiwanese cells in their modules, circumventing US trade duties.
Will this affect the Chinese PV module suppliers? Perhaps, not that much. Why so? China itself has a very huge domestic market for solar PV. They can continue to do well in China itself. It can also sell solar PV modules in India, as well, besides other regions in the Asia Pacific.
That brings me back to Intersolar North America 2014. Why was there such a low presence of Indian companies? The exhibitor list for the show reads only two — Lanco Solar Pvt Ltd and Vikram Solar Pvt Ltd. Where are the others?
If one looks at the Ministry for New and Renewable Energy (MNRE) website, there is a notification stating that a National Solar Mission (NSM) is being implemented to give a boost to solar power generation in the country. It has a long-term goal of adding 20,000 MWp of grid-connected solar power by 2022, to be achieved in three phases (first phase up to 2012-13, second phase from 2013 to 2017 and the third phase from 2017 to 2022).
Well, the MNRE has also put up a release stating complaints received about the non-function of the systems installed by channel partners. Without getting into details, why can’t Indian suppliers get to the ground and work up solidly? Some of the complaints are actually not even so serious. System not working. Channel partner not attending complaint! And, plant not working due to inverter (PPS) burnt down. These should be attended to quickly, unless, there is some monetary or other issue, which, at least, I am not aware of!
The CNA Corp.s Energy, Water, & Climate division released two studies earlier this week, which found that cost-effective options that power plants can use to cut water use can also help plants reduce CO2 emissions.
The first report, Capturing Synergies Between Water Conservation and Carbon Dioxide Emissions in the Power Sector, focuses on strategy recommendations based on analyses of water use and CO2 emissions in four case studies, which are detailed in the second report, A Clash of Competing Necessities: Water Adequacy and Electric Reliability in China, India, France, and Texas.
CNA’s Energy, Water, & Climate division released two studies, which found that cost-effective options that power plants can use to cut water use can also help plants reduce CO2 emissions.
“It’s a very important issue,” said lead study author Paul Faeth, director of Energy, Water, & Climate at CNA. “Water used to cool power plants is the largest source of water withdrawals in the United States and France, and a large source in China and India.”
“The recommendations in these reports can serve as a starting point for leaders in these countries, and for leaders around the world, to take the steps needed to ensure the reliability of current generating plants and begin planning for how to meet future demands for electric power.”
India needs to learn from the Intersolar North America show. It also needs to look carefully at CNA’s reports. It is always great and good work that attracts global attention. India has all of the requred capabilities to do so!
At the recently held Semicon West 2014, Daniel P. Tracy, senior director, Industry Research and Statistics, SEMI, presented on SEMI Materials Outlook. He estimated that semiconductor materials will see unit growth of 6 percent or more. There may be low revenue growth in a large number of segments due to the pricing pressures and change in material.
For semiconductor eequipment, he estimated ~20 percent growth this year, following two years of spending decline. It is currently estimated at ~11 percent spending growth in 2015.
Overall, the year to date estimate is positive growth vs. same period 2013, for units and materials shipments, and for equipment billings.
For equipment outlook, it is pointing to ~18 percent growth in equipment for 2014. Total equipment orders are up ~17 percent year-to-date.
For wafer fab materials outlook, the silicon area monthly shipments are at an all-time high for the moment. Lithography process chemicals saw -7 percent sales decline in 2013. The 2014 outlook is downward pressure on ASPs for some chemicals. 193nm resists are approaching $600 million. ARC has been growing 5-7 percent, respectively.
For packaging materials, the Flip Chip growth drivers are a flip chip growth of ~25 percent from 2012 to 2017 in units. There are trends toward copper pillar and micro bumps for TSV. Future flip chip growth in wireless products are driven by form factor and performance. BB and AP processors are also moving to flip chip.
There has been growth in WLP shipments. Major applications for WLP are driven by mobile products such as smartphones and tablets. It should grow at a CAGR of ~11 percent in units (2012-2017).
Solder balls were $280 million market in 2013. Shipments of lead-free solder balls continues to increase. Underfillls were $208 million in 2013. It includes underfills for flip chip and packages. The increased use of underfills for CSPs and WLPs are likely to pass the drop test in high-end mobile devices.
Wafer-level dielectrics were $94 million market in 2013. Materials and structures are likely to enhance board-level reliability performance.
Die-attach materials has over a dozen suppliers. Hitachi Chemical and Henkel account for major share of total die attach market. New players are continuing to emerge in China and Korea. Stacked-die CSP package applications have been increasing. Industry acceptance of film (flow)-over-wire (FOW) and dicing die attach film (DDF) technologies are also happening.
Christian Gregor Dieseldorff, senior analyst, Industry Research & Statistics Group at SEMI, presented the SEMI World Fab Forecast at the recently held Semicon West 2014, as part of the SEMI/Gartner Market Symposium on July 7.
Scenarios of fab equipment spending over time has been 20-25 percent in 2014, and 10-15 percent in 2015. At this time, worldwide fab equipment spending is about same in 1H14 vs 2H14. As for fab construction projects, 2013 was a record year with over $9 billion.
New fabs: construction spending (front end cleanrooms only!)
2013: record year with over $9 billion.
2014: -22 percent to -27 percent (~$6.6 billion)
2015: -22 percent to -30 percent (~$5 billion +/-).
Fab equipment spending front end (new and used)
2014: 20 percent to 25 percent (~$35 billion to $36 billion) – if $35 billion, then third largest on record.
2015: 10 percent to 15 percent (~$40 billion) – if $40 billion, then largest in record.
Installed capacity for front end fabs (without discretes)
2014: 2 to 3 percent
2015: 3 to 4 percent
Future outlook beyond 2015: less than 4 percent.
SEMI World Fab Forecast report status and activity outlined that there were 1,148 front end facilities (R&D to HVM) active and future. Also,
* There are 507 companies (R&D to HVM).
* Including 249 LEDs and Opto facilities active and future.
* There are 60 future facilities starting HVM in 2014 or later.
* Major investments (construction projects and/or equipping): 202 facilities in 2014, 189 facilities in 2015.
A slow down of fab closures is expected from 2015 to 2018 for 200mm fabs and 150mm fabs.
Renesas Electronics recently opened its India subsidiary in Bangalore. Elaborating, Sunil Dhar, managing director of Renesas Electronics India said: “We are glad to announce the opening of Renesas Electronics India Pvt Ltd, a wholly-owned subsidiary of Renesas Electronics Singapore Pte Ltd., located in Bangalore.
“Since 2010, Renesas has been providing technical product support to its customers here via branch offices in Bangalore, Delhi and Mumbai. As part of its expansion plan, Renesas will turn our said branches into a full subsidiary.
“The branch office setup served us well when the organization was small and its role was limited. In order to expand further in terms of opening more offices in India for close customer support, and to be able to provide wider services to customers in India like reference software, hardware, reference solutions which would be developed in India, it would require us to have a permanent establishment here.
“Through this new company, we aim to expand business by providing the best solution offerings and technical support as well as a regional systems solution development expertise to the Indian market.”
How does the India R&D team play a role in global innovation and where do you see Renesas Electronics in India five years from now?
He said that over 50 percent of the Renesas India team is application development or field engineers armed with knowledge of embedded hardware and software development and support.
In order to expand the footprint in Indian markets, Renesas plans to build up a strong application engineering team. India Application engineering team will engage with the Renesas headquarters, regional offices to develop new products and solutions dedicated for emerging countries, including India.
The application engineering team and the future solution centre aim to survey the market for solution needs, prepare India designed solutions fitting the price points and specifications points as required in the Indian market. Along with the customers, the team also intends to collaborate with the design houses to create innovative solutions addressing upcoming needs of the market. Our goal is to become the most trusted semiconductor solution provider in India.
What are the India-centric solutions that would be developed from the India Application Engineering team?
Dhar added that the needs of emerging markets are usually different in both specifications as well as price points. By providing dedicated local support via the new company, and with a focus on industrial and automotive applications for two- and four-wheelers, Renesas aims to increase its MCU share in India and expand its solution offerings with rich lineup of kit solutions (MCU + SoC + power devices) and platform reference boards (boards with complete ecosystem including devices and software) to provide customers a shorter time-to-market.
The team will initially focus on automotive and particularly, two-wheeler solutions. The intention is to expand the scope of the application engineering team’s activity to industrial and consumer appliances in near term.
What is the overall India employee strength? How are the investment plans looking up?
Dhar said: “In order to expand our footprint in Indian markets, we will double our headcount in near term. Currently, we are just under 30 staff and over 50 percent of us are application development or field engineers armed with the knowledge of embedded hardware and software development and support. Upon setting up the organization in Sales and Marketing roles in the initial days, we also have plans to announce the setting up of a Solutions Centre in India to develop reference application solutions to enable our customers to use our devices.
“We are intending to invest in lab, infrastructure setup and expansion of activities in the next three to five years. Additionally, we are also considering investing towards 3rd party and IDH for enlarged business engagement.”
Trends driving automotive market in India
Regarding trends driving the automotive market in India, Dhar said that Renesas focusses on three business segments – automotive, industrial and home, OA and ICT. Renesas holds more than 40 percent global market share for automotive MCU business. Our target applications for automotive segment are automotive control and automotive infotainment and network.
Renesas has dedication applications solutions for integrated cockpit through system on chip, R-car ecosystem collaboration solution for e-mobility and automotive analog and power devices for driving, steering and braking.
As semiconductor technologies evolved, it has enabled automakers to integrate multiple applications on a single chip significantly reducing the board area; thus optimizing performance and adding new features for comfort, safety and infotainment. Power technologies have brought energy efficiency, limiting power consumption in vehicles. Advancements in process technologies will continue to drive the auto industry in the coming years.
Renesas, for instance, developed the industry’s first 28nm flash memory IP for MCUs and the first semiconductor supplier to move from 40nm to 28nm process technology.
“Trends driving auto industry in India and globally are more of less the same. However, for India market, we see a specific demand for two-wheeler solutions and that is our target in coming years,” he concluded.
Lastly, I must take the opportunity to thank Ms Shweta Dhadiwal-Baid and Ms Sharmita Mandal for making this happen! 😉
Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. 😉 I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification mistakes.
Top verification mistakes
Kalia said that the biggest verification mistakes made today are:
* Verification engineers do not define a structured notion of verification completeness.
* Verification planning is not done up front and is carried out as verification is going along.
* A well-defined reusable verification methodology is not applied.
* Legacy tools continue to be used for verification; new tools and technologies are not adopted.
In that case, why are some companies STILL not knowing how to verify a chip?
He added: “I would not describe the situation as companies not knowing how to verify a chip. Instead, I think a more accurate description of the problem is that the verification complexity has increased so much that companies do not know how to meet their verification goals.
“For example, the number of cycles needed to verify a current generation processor – as calculated by traditional methods of doing verification – is too prohibitive to be done in any reasonable timeframe using legacy verification methodologies. Hence, new methodologies and tools are needed. Designs today need to be verified together with software. This also requires new tools and methodologies. Companies are not moving fast enough to define, adopt and use these new tools and methodologies thereby leading to challenges in verifying a chip.”
How are companies trying to address the challenges?
Companies are trying to address the challenges in various ways:
* Companies at the cutting edge of designs and verification are indeed trying to adopt structured verification methodologies to address these challenges.
* Smaller companies are trying to address these challenges by outsourcing their verification to experts and by hiring more verification experts.
* Verification acceleration and prototyping solutions are being adopted to get faster verification and which will allow companies to do more verification in the same amount of time.
* Verification environment re-use helps to cut down the time required to develop verification environments.
* Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.
Cadence has the widest portfolio of tools to help companies meet verification challenges, including:
Incisive Enterprise Manager, which provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility;
The recently launched vManager solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity;
Incisive Enterprise Verifier, which delivers dual power from tightly integrated formal analysis and simulation engines; and
Incisive Enterprise Simulator, which provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization.
Are companies building an infrastructure that gets you business advantage? Yes, companies are realizing the problems. It is these companies that are the winners in managing today’s design and verification challenges, he said.
When should good verification start?
Kalia noted: “Good verification should start right at the time of the high level architecture of the design. A verification strategy should be defined at that time, and an overall verification plan should be written at that time. This is where a comprehensive solution like Incisive vManager can help companies manage their verification challenges by ensuring that SoC developers have a consistent methodology for design quality enhancements.”
Are folks mistaking by looking at tools and not at the verification process itself?
He addded that right tools and methodology are needed to resolve today’s verification challenges. Users need to work on defining verification methodologies and at the same time look at the tools that are needed to achieve verification goals.
Finally, there’s verification planning! What should be the ‘right’ verification path?
Verification planning needs to include:
* A formal definition of verification goals;
* A formal definition of coverage goals at all levels – starting with code coverage all the way to functional coverage;
* Required resources – human and compute;
* Verification timelines;
* All the verification tools to be used for verification; and
* Minimum and maximum signoff criteria.
I recently met Sam Fuller, CTO, Analog Devices, and had an interesting conversation. First, I asked him about the state of the global semicon industry in 2013.
Industry in 2013
He said: “Due to the uncertainties in the global economy in the last couple of years, the state of the global semiconductor industry has been quite modest growth. Because of the modest growth, there has been a buildup in demand. As the global economies begin to be more robust going forward, we expect to see more growth.”
Industry in 2014?
How does Analog Devices see the industry going forward in 2014? What are the five key trends?
He added: “I would talk about the trends more from an eco-system and applications perspective. Increased capability on a single chip: Given all the advances to Moore’s law, the capability of a chip has increased considerably in all dimensions and not just performance, be it the horsepower we see in today’s smartphones or the miniaturization and power consumption of wearable gadgets that were on show this year at CES.
“In Analog Devices’ case, as we are focused on high performance signal processing, we can put more of the entire signal chain on a single die. For our customers, the challenge is to provide their customers a more capable product which means a more complex product, but with a simpler interface.
“A classic example is our AD9361 chip, which is a single chip wideband radio transceiver for Software Defined Radio (SDR). It is a very capable ASSP (Application Specific Standard Products) as well as RF front end with a wide operating frequency of 70 MHz to 6 GHz.
“This chip, coupled with an all-purpose FPGA, can build a very flexible SDR operating across different radio protocols, wide frequency range and bandwidth requirements all controlled via software configuration. It finds a number of applications in wireless communication infrastructure, small cell Base stations as well as a whole range of custom radios in the industrial and aerospace businesses.”
Now, let’s see the trends for 2014!
More collaboration with customers: There is a greater emphasis on understanding customers’ end applications to provide a complete signal chain, all in a System on a Chip (SoC) or a System in a package (SiP). The relationship with our customers is changing as we move more towards ASSPs focused with few lead customers for target markets and target applications. While this has already been ongoing in the consumer industry with PCs and laptops, customers in other vertical markets like healthcare, automotive and industrial are and will collaborate more with semiconductor companies like Analog Devices to innovate at a solutions level.
More complete products: We have evolved from delivering just the silicon at a component level to delivering more complete products with more advanced packaging for various 3D chips or multi-die within a package. Our solutions now have typically much more software that makes it easier to configure or program the chips. It is a solution that is a combination of more advanced silicon, advanced packaging and more appropriate software.
With providing the complete solution, the products are more application specific and hence, the need for more collaboration with customers. For example, there may be one focused on Software Defined Radio, one for motor control, and one for vital signs monitoring for consumer health that we have launched recently.
We need it to be generic enough that multiple customers can use it, but it needs to be as tailored as possible to the customers’ needs for specific market segments. While because of the volume and standardization, availability of complete reference designs in the consumer world has been the norm, other market segments are demanding more complete products not-withstanding the huge variation in protocols and applications.
Truly global industry: The semiconductor and electronics industry has become truly global, so multiple design sites around the globe collaborate to create products. For example for Analog Devices, one of our premier design sites is our Bangalore product design center where we quite literally developed our most complex and capable chips. At the same time our customers are also global.
We see large multinational companies like GE, Honeywell, Cisco, Juniper, ABB, Schneider and many of our top strategic customers globally doing substantial system design work in Bangalore along with a multitude of India design houses. Our fastest growing region is in Asia, but we have substantial engagement with customers in North America and Europe. And our competition is also global, which means that the industry is ever moving faster as the competition is global.
Smarter design tools: The final trend worth talking about is the need for smarter design tools. As our products and our customers’ products become more complex and capable, there have to be rapidly developing design tools, for us to design them.
This cannot be done by brute force but by designing smarter and better tools. There is a lot of innovation that goes on in developing better tool suites. There is also ever more capable software that caters to a market moving from 100s of transistors to literally billions of transistors for an application.